VHDL Operators

Constants in VHDL

Constants in VHDL can be declared in any declarative region, and can be used within that region. Their value cannot be changed once declared.

signal sig1 : std_logic_vector (5 downto 0);

constant init0 : std_logic_vector (5 downto 0) := "010111"; sig1 <= init0;

VHDL Operators

Supported operators are listed in Table 6-21, “VHDL Operators.” This section provides examples of how to use each shift operator.

Operators VHDL Coding Example One

sll (Shift Left Logical)

sig1 <= A(4 downto 0) sll 2

logically equivalent to:

sig1 <= A(2 downto 0) & "00";

Operators VHDL Coding Example Two

srl (Shift Right Logical)

sig1 <= A(4 downto 0) srl 2

logically equivalent to:

sig1 <= "00" & A(4 downto 2);

Operators VHDL Coding Example Three

sla (Shift Left Arithmetic)

sig1 <= A(4 downto 0) sla 2

logically equivalent to:

sig1 <= A(2 downto 0) & A(0) & A(0);

Operators VHDL Coding Example Four

sra (Shift Right Arithmetic)

sig1 <= A(4 downto 0) sra 2

logically equivalent to:

sig1 <= <= A(4) & A(4) & A(4 downto 2);

Operators VHDL Coding Example Five

rol (Rotate Left)

sig1 <= A(4 downto 0) rol 2

logically equivalent to:

sig1 <= A(2 downto 0) & A(4 downto 3);

10.1