Use DSP48 Propagation Rules

Use DSP48 applies to an entity, component, module, or signal to which it is attached.

Use DSP48 Syntax Examples

Following are syntax examples using Use DSP48 with particular tools or methods. If a tool or method is not listed, Use DSP48 may not be used with it.

Use DSP48 VHDL Syntax Example

Before using Use DSP48, declare it with the following syntax:

attribute use_dsp48: string;

After declaring Use DSP48, specify the VHDL constraint:

attribute use_dsp48 of {entity_name|component_name|signal_name}: {entity|component|signal} is "{auto|yes|no}";

Use DSP48 Verilog Syntax Example

Place Use DSP48 immediately before the module or signal declaration:

(* use_dsp48 = "{auto|yes|no}" *)

Use DSP48 XCF Syntax Example One

MODEL "entity_name" use_dsp48={auto|yes|no|true|false};

Use DSP48 XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" use_dsp48={auto|yes|no|true|false};

END;

Use DSP48 XST Command Line Syntax Example

Define Use DSP48 globally with the –use_dsp48 command line option of the run command:

Use DSP48 Project Navigator Syntax Example

Define Use DSP48 globally in Project Navigator > Process Properties > HDL Options > Use DSP48.

XST CPLD Constraints (Non-Timing)

The section discusses XST CPLD constraints (non-timing). The constraints in this section apply to CPLD devices only. They do not apply to FPGA devices. This section discusses the following constraints:

•“Clock Enable (–pld_ce)”

•“Data Gate (DATA_GATE)”

•“Macro Preserve (–pld_mp)”

•“No Reduce (NOREDUCE)”

•“WYSIWYG (–wysiwyg)”

•“XOR Preserve (–pld_xp)”

Clock Enable (–pld_ce)

Clock Enable (-pld_ce) specifies how sequential logic should be implemented when it contains a clock enable, either using the specific device resources available for that or generating equivalent logic.

Clock Enable allows you to specify the way the clock enable function is implemented if presented in the design.

Clock Enable values are:

•yes

The synthesizer implements the clock enable signal of the device.

•no

The clock enable function is implemented through equivalent logic.

Keeping or not keeping the clock enable signal depends on the design logic. Sometimes, when the clock enable is the result of a Boolean expression, setting Clock Enable to no may improve the fitting result. The input data of the flip-flop is simplified when it is merged with the clock enable expression.

Clock Enable Architecture Support

Clock Enable applies to all CPLD devices. Clock Enable does not apply to FPGA devices.

Clock Enable Applicable Elements

Clock Enable applies to an entire design through the XST command line.

Clock Enable Propagation Rules

Not applicable

Clock Enable Syntax Examples

Following are syntax examples using Clock Enable with particular tools or methods. If a tool or method is not listed, Clock Enable may not be used with it.

Clock Enable XST Command Line Syntax Example

Define Clock Enable globally with the –pld_ce command line option of the run command:

-pld_ce {yes|no}

The default is yes.

Clock Enable Project Navigator Syntax Example

Define Clock Enable globally in Project Navigator > Process Properties > Xilinx-Specific Options > Clock Enable.

Data Gate (DATA_GATE)

Data Gate applies to CoolRunner-II devices only.

Data Gate (DATA_GATE) provides direct means of reducing power consumption in your design. Each I/O pin input signal passes through a latch that can block the propagation of

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incident transitions during periods when such transitions are not of interest to your CPLD design.

Input transitions that do not affect the CPLD design function still consume power, if not latched, as they are routed among the CPLD's Function Blocks. By asserting the Data Gate control I/O pin on the device, selected I/O pin inputs become latched, thereby eliminating the power dissipation associated with external transitions on those pins.

For more information, see “DATA_GATE” in the Xilinx Constraints Guide.

Macro Preserve (–pld_mp)

Macro Preserve (-pld_mp) makes macro handling independent of design hierarchy processing. This allows you to merge all hierarchical blocks in the top module, while still keeping the macros as hierarchical modules. You can also keep the design hierarchy except for the macros, which are merged with the surrounding logic. Merging the macros sometimes gives better results for design fitting.

Macro Preserve values are:

•yes

Macros are preserved and generated by Macro+.

•no

Macros are rejected and generated by HDL synthesizer

Depending on the Macro Preserve value, a rejected macro is either merged in the design logic, or becomes a hierarchical block. See Table 5-7, “Disposition of Rejected Macros.”

Table 5-7: Disposition of Rejected Macros

Very small macros such as 2-bit adders and 4-bit multiplexers are always merged, independent of the Macro Preserve or Flatten Hierarchy options.

Macro Preserve Architecture Support

Macro Preserve applies to all CPLD devices. Macro Preserve does not apply to FPGA devices.

Macro Preserve Applicable Elements

Macro Preserve applies to an entire design through the XST command line.

Macro Preserve Propagation Rules

Not applicable

Macro Preserve Syntax Examples

Following are syntax examples using Macro Preserve with particular tools or methods. If a tool or method is not listed, Macro Preserve may not be used with it.

Macro Preserve XST Command Line Syntax Example

Define Macro Preserve globally with the –pld_mp command line option of the run command:

-pld_mp {yes|no}

The default is yes.

Macro Preserve Project Navigator Syntax Example

Define Macro Preserve globally in Project Navigator > Process Properties > Xilinx-Specific Options > Macro Preserve.

No Reduce (NOREDUCE)

No Reduce (NOREDUCE):

•Prevents minimization of redundant logic terms that are typically included in a design to avoid logic hazards or race conditions

•Identifies the output node of a combinatorial feedback loop to ensure correct mapping

For more information, see “NOREDUCE” in the Xilinx Constraints Guide.

WYSIWYG (–wysiwyg)

WYSIWYG (–wysiwyg) makes a netlist reflect the user specification as closely as possible. That is, all the nodes declared in the Hardware Description Language (HDL) design are preserved.

If WYSIWYG mode is enabled (yes), XST:

•Preserves all user internal signals (nodes)

•Creates SOURCE_NODE constraints in the NGC file for all these nodes

•Skips design optimization (collapse, factorization)

Only boolean equation minimization is performed.

WYSIWYG Architecture Support

WYSIWYG applies to all CPLD devices. WYSIWYG does not apply to FPGA devices.

WYSIWYG Applicable Elements

WYSIWYG applies to an entire design through the XST command line.

WYSIWYG Propagation Rules

Not applicable

WYSIWYG Syntax Examples

Following are syntax examples using WYSIWYG with particular tools or methods. If a tool or method is not listed, WYSIWYG may not be used with it.

WYSIWYG XST Command Line Syntax Example

Define WYSIWYG globally with the –wysiwyg command line option of the run command:

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