Keep Hierarchy Syntax Examples

Following are syntax examples using Keep Hierarchy with particular tools or methods. If a tool or method is not listed, Keep Hierarchy may not be used with it.

Keep Hierarchy Schematic Syntax Example

•Attach to the entity or module symbol.

•Attribute Name: KEEP_HIERARCHY

•Attribute Values: YES, NO

Keep Hierarchy VHDL Syntax Example

Before using Keep Hierarchy, declare it with the following syntax:

attribute keep_hierarchy : string;

After declaring Keep Hierarchy, specify the VHDL constraint:

attribute keep_hierarchy of architecture_name: architecture is "{yes|no|true|false|soft}";

The default is no for FPGA devices and yes for CPLD devices.

Keep Hierarchy Verilog Syntax Example

Place this attribute immediately before the module declaration or instantiation:

(* keep_hierarchy = "{yes|no|true|false|soft}" *)

Keep Hierarchy XCF Syntax Example

MODEL "entity_name" keep_hierarchy={yes|no|true|false|soft};

Keep Hierarchy XST Command Line Syntax Example

Define Keep Hierarchy globally with the -keep_hierarchy command line option of the run command:

-keep_hierarchy {yes|no|soft}

The default is no for FPGA devices and yes for CPLD devices.

For more information, see “XST Command Line Mode.”

Keep Hierarchy Project Navigator Syntax Example

Define Keep Hierarchy globally in Project Navigator > Process Properties > Synthesis Options > Keep Hierarchy.

Library Search Order (–lso)

Use Library Search Order (-lso) to specify the order in which library files are used. To invoke Library Search Order:

•Specify the search order file in Project Navigator > Process Properties >

Synthesis Options > Library Search, or

•Use the –lso command line option

Library Search Order Architecture Support

Library Search Order is architecture independent.

10.1

Library Search Order Applicable Elements

Library Search Order applies to files.

Library Search Order Propagation Rules

Not applicable

Library Search Order Syntax Examples

Following are syntax examples using Library Search Order with particular tools or methods. If a tool or method is not listed, Library Search Order may not be used with it.

Library Search Order XST Command Line Syntax Example

Define Library Search Order globally with the –lso command line option of the run command:

-lso file_name.lso

There is no default file name. If not specified, XST uses the default search order.

For more information, see the “Library Search Order (LSO) Files in Mixed Language

Projects.”

Library Search Order Project Navigator Syntax Example

Define Library Search Order globally in Project Navigator > Process

Properties > Synthesis Options > Library Search Order.

For more information, see “Library Search Order (LSO) Files in Mixed Language Projects.”

LOC

The LOC constraint defines where a design element can be placed within an FPGA or

CPLD device. For more information, see “LOC” in the Xilinx Constraints Guide.

Netlist Hierarchy (-netlist_hierarchy)

Use Netlist Hierarchy (-netlist_hierarchy) to control the form in which the final NGC netlist is generated. Netlist Hierarchy allows you to write the hierarchical netlist even if the optimization was done on a partially or fully flattened design.

If the value of Netlist Hierarchy is:

•as_optimized

XST takes into account the “Keep Hierarchy (KEEP_HIERARCHY)” constraint, and generates the NGC netlist in the form in which it was optimized. In this mode, some hierarchical blocks can be flattened, and some can maintain hierarchy boundaries.

•rebuilt

XST writes a hierarchical NGC netlist, regardless of the “Keep Hierarchy (KEEP_HIERARCHY)” constraint.

Netlist Hierarchy Architecture Support

Netlist Hierarchy is architecture independent.

Netlist Hierarchy Applicable Elements

Netlist Hierarchy applies globally.

Netlist Hierarchy Propagation Rules

Not applicable

Netlist Hierarchy Syntax Examples

Following are syntax examples using Netlist Hierarchy with particular tools or methods. If a tool or method is not listed, Netlist Hierarchy may not be used with it.

Netlist Hierarchy XST Command Line Syntax Example

Define Netlist Hierarchy globally with the – netlist_hierarchy command line option of the run command:

- netlist_hierarchy { as_optimized|rebuilt }

The default is as_optimized.

Optimization Effort (OPT_LEVEL)

Optimization Effort (OPT_LEVEL) defines the synthesis optimization effort level.

Allowed Optimization Effort values are:

•1 (normal optimization)

Use 1 (normal optimization) for very fast processing, especially for hierarchical designs. In speed optimization mode, Xilinx recommends using 1 (normal optimization) for the majority of designs. 1 (normal optimization) is the default.

•2 (higher optimization)

While 2 (higher optimization) is more time consuming, it sometimes gives better results in the number of slices/macrocells or maximum frequency. Selecting 2 (higher optimization) usually results in increased synthesis run times, and does not always bring optimization gain.

Optimization Effort Architecture Support

Optimization Effort is architecture independent.

Optimization Effort Applicable Elements

Optimization Effort applies globally, or to an entity or module.

Optimization Effort Propagation Rules

Optimization Effort applies to the entity or module to which it is attached.

Optimization Effort Syntax Examples

Following are syntax examples using Optimization Effort with particular tools or methods. If a tool or method is not listed, Optimization Effort may not be used with it.

10.1

Optimization Effort VHDL Syntax Example

Before using Optimization Effort, declare it with the following syntax:

attribute opt_level: string;

After declaring Optimization Effort, specify the VHDL constraint:

attribute opt_level of entity_name: entity is "{1|2}";

Optimization Effort Verilog Syntax Example

Place this attribute immediately before the module declaration or instantiation:

(* opt_level = "{1|2}" *)

Optimization Effort XCF Syntax Example

MODEL "entity_name" opt_level={1|2};

Optimization Effort XST Command Line Syntax Example

Define Optimization Effort globally with the –opt_level command line option:

-opt_level {1|2}

The default is 1.

Optimization Effort Project Navigator Syntax Example

Define Optimization Effort globally in Project Navigator > Process Properties > Synthesis Options > Optimization Effort.

Optimization Goal (OPT_MODE)

Optimization Goal (OPT_MODE defines the synthesis optimization strategy.

Available Optimization Goal values are:

•speed

The priority of speed is to reduce the number of logic levels and therefore to increase frequency. speed is the default.

•area

The priority of area is to reduce the total amount of logic used for design implementation and therefore improve design fitting.

Optimization Goal Architecture Support

Optimization Goal is architecture independent.

Optimization Goal Applicable Elements

Optimization Goal applies globally, or to an entity or module.

Optimization Goal Propagation Rules

Optimization Goal applies to the entity or module to which it is attached.