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Decoders HDL Coding Techniques
3-to-1 1-Bit MUX With 1-Bit Latch Verilog Coding Example
//
// 3-to-1 1-bit MUX with a 1-bit latch.
//
module v_multiplexers_4 (a, b, c, s, o); input a,b,c;
input [1:0] s; output o;
reg o;
always @(a or b or c or s) begin
if (s == 2'b00) o = a; else if (s == 2'b01) o = b; else if (s == 2'b10) o = c;
end endmodule
Decoders HDL Coding Techniques
This section discusses Decoders HDL Coding Techniques, and includes:
•“About Decoders”
•“Decoders Log File”
•“Decoders Related Constraints”
•“Decoders Coding Examples”
About Decoders
A decoder is a multiplexer whose inputs are all constant with distinct one-hot (or one-cold) coded values. For more information, see “Multiplexers HDL Coding Techniques.”
Decoders Log File
The XST log file reports the type and size of recognized decoders during the Macro
Recognition step.
Synthesizing Unit <dec>.
Related source file is decoders_1.vhd. Found 1-of-8 decoder for signal <res>. Summary:
inferred 1 Decoder(s). Unit <dec> synthesized.
==============================
HDL Synthesis Report |
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# Decoders |
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1-of-8 decoder |
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Decoders Related Constraints
•“Decoder Extraction (DECODER_EXTRACT)”
Decoders Coding Examples
The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip
•“1-of-8 Decoder (One-Hot)”
•“1-of-8 Decoder (One-Cold)”
•“Decoder With Unselected Outputs”
1-of-8 Decoder (One-Hot)
This section discusses 1-of-8 Decoder (One-Hot), and includes:
•“1-of-8 Decoder (One-Hot) Diagram”
•“1-of-8 Decoders (One-Hot) Pin Descriptions”
•“1-of-8 Decoder (One-Hot) VHDL Coding Example”
•“1-of-8 decoder (One-Hot) Verilog Coding Example”
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Figure 2-35: 1-of-8 Decoder (One-Hot) Diagram |
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Table 2-38: 1-of-8 Decoders (One-Hot) Pin Descriptions |
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IO Pins |
Description |
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Selector |
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1-of-8 Decoder (One-Hot) VHDL Coding Example
--
-- 1-of-8 decoder (One-Hot)
--
library ieee;
use ieee.std_logic_1164.all;
entity decoders_1 is
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Decoders HDL Coding Techniques
port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0));
end decoders_1;
architecture archi of decoders_1 is begin
res <= "00000001" when sel = "000" else "00000010" when sel = "001" else "00000100" when sel = "010" else "00001000" when sel = "011" else "00010000" when sel = "100" else "00100000" when sel = "101" else "01000000" when sel = "110" else "10000000";
end archi;
1-of-8 decoder (One-Hot) Verilog Coding Example
//
// 1-of-8 decoder (One-Hot)
//
module v_decoders_1 (sel, res); input [2:0] sel;
output [7:0] res; reg [7:0] res;
always @(sel or res) begin
case (sel)
3'b000 : res = 8'b00000001; 3'b001 : res = 8'b00000010; 3'b010 : res = 8'b00000100; 3'b011 : res = 8'b00001000; 3'b100 : res = 8'b00010000; 3'b101 : res = 8'b00100000; 3'b110 : res = 8'b01000000; default : res = 8'b10000000;
endcase
end endmodule
1-of-8 Decoder (One-Cold)
This section discusses 1-of-8 Decoder (One-Cold), and includes:
•“1-of-8 Decoder (One-Cold) Pin Descriptions”
•“1-of-8 decoder (One-Cold) VHDL Coding Example”
•“1-of-8 Decoder (One-Cold) Verilog Coding Example”
Table 2-39: 1-of-8 Decoder (One-Cold) Pin Descriptions
IO Pins |
Description |
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s |
Selector |
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res |
Data Output |
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1-of-8 decoder (One-Cold) VHDL Coding Example
--
-- 1-of-8 decoder (One-Cold)
--
library ieee;
use ieee.std_logic_1164.all;
entity decoders_2 is
port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0));
end decoders_2;
architecture archi of decoders_2 is begin
res <= "11111110" when sel = "000" else "11111101" when sel = "001" else "11111011" when sel = "010" else "11110111" when sel = "011" else "11101111" when sel = "100" else "11011111" when sel = "101" else "10111111" when sel = "110" else "01111111";
end archi;
1-of-8 Decoder (One-Cold) Verilog Coding Example
//
// 1-of-8 decoder (One-Cold)
//
module v_decoders_2 (sel, res); input [2:0] sel;
output [7:0] res; reg [7:0] res;
always @(sel) begin
case (sel)
3'b000 : res = 8'b11111110; 3'b001 : res = 8'b11111101; 3'b010 : res = 8'b11111011; 3'b011 : res = 8'b11110111; 3'b100 : res = 8'b11101111; 3'b101 : res = 8'b11011111; 3'b110 : res = 8'b10111111; default : res = 8'b01111111;
endcase
end endmodule
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Decoders HDL Coding Techniques
Decoder With Unselected Outputs
This section discusses Decoder With Unselected Outputs, and includes:
•“Decoder With Unselected Outputs Pin Descriptions”
•“No Decoder Inference (Unused Decoder Output) VHDL Coding Example”
•“No Decoder Inference (Unused Decoder Output) Verilog Coding Example”
•“No Decoder Inference (Some Selector Values Unused) VHDL Coding Example”
•“No Decoder Inference (Some Selector Values Unused) Verilog Coding Example”
Table 2-40: Decoder With Unselected Outputs Pin Descriptions
IO Pins |
Description |
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s |
Selector |
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res |
Data Output |
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No Decoder Inference (Unused Decoder Output) VHDL Coding Example
--
-- No Decoder Inference (unused decoder output)
--
library ieee;
use ieee.std_logic_1164.all;
entity decoders_3 is
port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0));
end decoders_3;
architecture archi of decoders_3 is begin
res <= "00000001" when sel = "000" else -- unused decoder output "XXXXXXXX" when sel = "001" else "00000100" when sel = "010" else "00001000" when sel = "011" else "00010000" when sel = "100" else "00100000" when sel = "101" else "01000000" when sel = "110" else "10000000";
end archi;
No Decoder Inference (Unused Decoder Output) Verilog Coding Example
//
// No Decoder Inference (unused decoder output)
//
module v_decoders_3 (sel, res); input [2:0] sel;
output [7:0] res; reg [7:0] res;
always @(sel) begin
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case (sel)
3'b000 : res = 8'b00000001; // unused decoder output 3'b001 : res = 8'bxxxxxxxx; 3'b010 : res = 8'b00000100; 3'b011 : res = 8'b00001000; 3'b100 : res = 8'b00010000; 3'b101 : res = 8'b00100000; 3'b110 : res = 8'b01000000; default : res = 8'b10000000;
endcase
end endmodule
No Decoder Inference (Some Selector Values Unused) VHDL Coding Example
--
-- No Decoder Inference (some selector values are unused)
--
library ieee;
use ieee.std_logic_1164.all;
entity decoders_4 is
port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0));
end decoders_4;
architecture archi of decoders_4 is begin
res <= "00000001" when sel = "000" else "00000010" when sel = "001" else "00000100" when sel = "010" else "00001000" when sel = "011" else "00010000" when sel = "100" else "00100000" when sel = "101" else
-- 110 and 111 selector values are unused "XXXXXXXX";
end archi;
No Decoder Inference (Some Selector Values Unused) Verilog Coding Example
//
// No Decoder Inference (some selector values are unused)
//
module v_decoders_4 (sel, res); input [2:0] sel;
output [7:0] res; reg [7:0] res;
always @(sel or res) begin
case (sel)
3’b000 : res = 8’b00000001; 3’b001 : res = 8’b00000010; 3’b010 : res = 8’b00000100; 3’b011 : res = 8’b00001000;
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