VHDL Attribute Syntax

You can describe constraints with VHDL attributes in the VHDL code. Before it can be used, an attribute must be declared with the following syntax:

attribute AttributeName : Type ;

VHDL Attribute Syntax Example One

attribute RLOC : string ;

The attribute type defines the type of the attribute value. The only allowed type for XST is string. An attribute can be declared in an entity or architecture. If declared in the entity, it is visible both in the entity and the architecture body. If the attribute is declared in the architecture, it cannot be used in the entity declaration. Once declared a VHDL attribute can be specified as follows:

attribute AttributeName of ObjectList : ObjectType is AttributeValue ;

VHDL Attribute Syntax Example Two

attribute RLOC of u123 : label is R11C1.S0 ; attribute bufg of my_signal : signal is sr;

The object list is a comma separated list of identifiers. Accepted object types are entity, component, label, signal, variable and type.

Follow these general rules:

•If a constraint can be applied on an entity (VHDL), then it can also be applied on the component declaration. The ability to apply constraints on components is not explicitly stated for each individual constraint, since it is a general XST rule.

•Some third party synthesis tools allow you to apply constraints on architectures. XST allows constraints on architectures only for those third party constraints automatically supported by XST.

Verilog-2001 Attributes

This section discusses Verilog-2001 Attributes, and includes:

•“About Verilog-2001 Attributes”

•“Verilog-2001 Attributes Syntax”

•“Verilog-2001 Limitations”

•“Verilog-2001 Meta Comments”

About Verilog-2001 Attributes

XST supports Verilog-2001 attribute statements. Attributes are comments that pass specific information to software tools such as synthesis tools. Verilog-2001 attributes can be specified anywhere for operators or signals within module declarations and instantiations. Other attribute declarations may be supported by the compiler, but are ignored by XST.

Use attributes to:

•Set constraints on individual objects (for example, module, instance, net)

•Set the “Full Case (FULL_CASE)” and “Parallel Case (PARALLEL_CASE)” synthesis constraints

Verilog-2001 Attributes Syntax

Attributes are bounded by asterisks (*), and use the following syntax:

(* attribute_name = attribute_value *)

where

•The attribute precedes the signal, module, or instance declaration to which it refers.

•The attribute_value is a string. No integer or scalar values are allowed.

•The attribute_value is between quotes.

•The default is 1. (* attribute_name *) is the same as

(* attribute_name = "1" *).

Verilog-2001 Attributes Syntax Example One

(* clock_buffer = "IBUFG" *) input CLK;

Verilog-2001 Attributes Syntax Example Two

(* INIT = "0000" *) reg [3:0] d_out;

Verilog-2001 Attributes Syntax Example Three

always@(current_state or reset)

begin (* parallel_case *) (* full_case *) case (current_state)

...

Verilog-2001 Attributes Syntax Example Four

(* mult_style = "pipe_lut" *) MULT my_mult (a, b, c);

Verilog-2001 Limitations

Verilog-2001 attributes are not supported for:

•Signal declarations

•Statements

•Port connections

•Expression operators

Verilog-2001 Meta Comments

Constraints can also be specified in Verilog code using meta comments. The Verilog-2001 format is the preferred syntax, but the meta comment style is still supported. Use the following syntax:

// synthesis attribute AttributeName [of] ObjectName [is] AttributeValue

Examples

//synthesis attribute RLOC of u123 is R11C1.S0

//synthesis attribute HU_SET u1 MY_SET

//synthesis attribute bufg of my_clock is "clk"

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