About Behavioral Verilog Variable Declarations

Variables in Verilog may be declared as integers or real. These declarations are intended for use in test code only. Verilog provides data types such as reg and wire for actual hardware description.

The difference between reg and wire is whether the variable is given its value in a procedural block (reg) or in a continuous assignment (wire) Verilog code. Both reg and wire have a default width being one bit wide (scalar). To specify an N-bit width (vectors) for a declared reg or wire, the left and right bit positions are defined in square brackets separated by a colon. In Verilog-2001, both reg and wire data types can be signed or unsigned.

Behavioral Verilog Variable Declarations Coding Examples

This section gives the following Behavioral Verilog Variable Declarations coding examples:

•“Behavioral Verilog Variable Declarations Coding Example”

Behavioral Verilog Variable Declarations Coding Example

reg [3:0] arb_priority; wire [31:0] arb_request;

wire signed [8:0] arb_signed;

where

•arb_request[31] is the MSB

•arb_request[0] is the LSB

Behavioral Verilog Initial Values

This section discusses Behavioral Verilog Initial Values, and includes:

•“About Behavioral Verilog Initial Values”

•“Behavioral Verilog Initial Values Coding Examples”

About Behavioral Verilog Initial Values

In Verilog-2001, you can initialize registers when you declare them.

The value:

•Is a constant

•Cannot depend on earlier initial values

•Cannot be a function or task call

•Can be a parameter value propagated to the register

•Specifies all bits of a vector