XST Timing Constraints

XOR Preserve Syntax Examples

Following are syntax examples using XOR Preserve with particular tools or methods. If a tool or method is not listed, XOR Preserve may not be used with it.

XOR Preserve XST Command Line Syntax Example

Define XOR Preserve globally with the –pld_xp command line option of the run command:

-pld_xp {yes|no}

The default is yes.

XOR Preserve Project Navigator Syntax Example

Define XOR Preserve globally in Project Navigator > Process Properties > Xilinx-Specific Options > XOR Preserve.

XST Timing Constraints

This section discusses XST timing constraints:

•“Cross Clock Analysis (–cross_clock_analysis)”

•“Write Timing Constraints (–write_timing_constraints)”

•“Clock Signal (CLOCK_SIGNAL)”

•“Global Optimization Goal (–glob_opt)”

•“XCF Timing Constraint Support”

•“Period (PERIOD)”

•“Offset (OFFSET)”

•“From-To (FROM-TO)”

•“Timing Name (TNM)”

•“Timing Name on a Net (TNM_NET)”

•“Timegroup (TIMEGRP)”

•“Timing Ignore (TIG)”

Applying Timing Constraints

Apply XST-supported timing constraints with:

•Global Optimization Goal (-glob_opt)

•Project Navigator > Process Properties > Synthesis Options > Global Optimization Goal

•User Constraints File (UCF)

Applying Timing Constraints Using Global Optimization Goal

Global Optimization Goal (-glob_opt) allows you to apply the five global timing constraints:

•ALLCLOCKNETS

•OFFSET_IN_BEFORE

•OFFSET_OUT_AFTER

10.1

•INPAD_TO_OUTPAD

•MAX_DELAY

These constraints are applied globally to the entire design. You cannot specify a value for these constraints, since XST optimizes them for the best performance. These constraints are overridden by constraints specified in the User Constraints File (UCF).

Applying Timing Constraints Using the User Constraints File (UCF)

The User Constraints File (UCF allows you to specify timing constraints using native UCF syntax. XST supports constraints such as:

•“Timing Name (TNM)”

•“Timegroup (TIMEGRP)”

•“Period (PERIOD)”

•“Timing Ignore (TIG)”

•“From-To (FROM-TO)”

XST supports wildcards and hierarchical names with these constraints.

Writing Constraints to the NGC file

Timing constraints are not written to the NGC file by default. Timing constraints are written to the NGC file only when:

•Write Timing Constraints is checked yes in Project Navigator > Process Properties, or

•The -write_timing_constraints option is specified when using the command line.

Additional Options Affecting Timing Constraint Processing

Three additional options affect timing constraint processing, regardless of how the timing constraints are specified:

•“Cross Clock Analysis (–cross_clock_analysis)”

•“Write Timing Constraints (–write_timing_constraints)”

•“Clock Signal (CLOCK_SIGNAL)”

Cross Clock Analysis (–cross_clock_analysis)

Cross Clock Analysis (-cross_clock_analysis) allows inter-clock domain analysis during timing optimization. By default (no), XST does not perform this analysis.

Cross Clock Analysis Architecture Support

Cross Clock Analysis applies to all FPGA devices. Cross Clock Analysis does not apply to CPLD devices.

Cross Clock Analysis Applicable Elements

Cross Clock Analysis applies to an entire design through the XST command line.

Cross Clock Analysis Propagation Rules

Not applicable

Cross Clock Analysis Syntax Examples

Following are syntax examples using Cross Clock Analysis with particular tools or methods. If a tool or method is not listed, Cross Clock Analysis may not be used with it.

Cross Clock Analysis XST Command Line Syntax Example

Define Cross Clock Analysis globally with the –cross_clock_analysis command line option of the run command:

-cross_clock_analysis {yes|no}

The default is yes.

Cross Clock Analysis Project Navigator Syntax Example

Define Cross Clock Analysis globally in Project Navigator > Process

Properties > Synthesis Options > Cross Clock Analysis.

Write Timing Constraints (–write_timing_constraints)

Timing constraints are written to the NGC file only when:

•Write Timing Constraints is checked yes in Project Navigator > Process Properties, or

•The -write_timing_constraints option is specified when using the command line.

Timing constraints are not written to the NGC file by default.

Write Timing Constraints Architecture Support

Write Timing Constraints is architecture independent.

Write Timing Constraints Applicable Elements

Write Timing Constraints applies to an entire design through the XST command line.

Write Timing Constraints Propagation Rules

Not applicable

Write Timing Constraints Syntax Examples

Following are syntax examples using Write Timing Constraints with particular tools or methods. If a tool or method is not listed, Write Timing Constraints may not be used with it.

Write Timing Constraints XST Command Line Syntax Example

Define Write Timing Constraints globally with the –write_timing_constraints command line option of the run command:

-write_timing_constraints {yes|no}

The default is yes.

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If a clock signal goes through combinatorial logic before being connected to the clock input of a flip-flop, XST cannot identify what input pin or internal signal is the real clock signal. Clock Signal (CLOCK_SIGNAL) allows you to define the clock signal.

Clock Signal Architecture Support

Clock Signal applies to all FPGA devices. Clock Signal does not apply to CPLD devices.

Clock Signal Applicable Elements

Clock Signal applies to signals.

Clock Signal Propagation Rules

Clock Signal applies to clock signals.

Clock Signal Syntax Examples

Following are syntax examples using Clock Signal with particular tools or methods. If a tool or method is not listed, Clock Signal may not be used with it.

Clock Signal VHDL Syntax Example

Before using Clock Signal, declare it with the following syntax:

attribute clock_signal : string;

After declaring CLOCK_SIGNAL, specify the VHDL constraint:

attribute clock_signal of signal_name : signal is “{yes|no}”;

Clock Signal Verilog Syntax Example

Place Clock Signal immediately before the signal declaration:

(* clock_signal = "{yes|no}" *)

Clock Signal XCF Syntax Example

BEGIN MODEL "entity_name"

NET "primary_clock_signal" clock_signal={yes|no|true|false};

END;

Global Optimization Goal (–glob_opt)

Depending on the Global Optimization Goal, XST can optimize the following design regions:

•Register to register

•Inpad to register

•Register to outpad

•Inpad to outpad)

Global Optimization Goal (-glob_opt) selects the global optimization goal. For a detailed description of supported timing constraints, see “Partitions.”

You cannot specify a value for Global Optimization Goal. XST optimizes the entire design for the best performance.

Apply the following constraints with Global Optimization Goal:

•ALLCLOCKNETS

Optimizes the period of the entire design

•OFFSET_IN_BEFORE

Optimizes the maximum delay from input pad to clock, either for a specific clock or for an entire design

•OFFSET_OUT_AFTER

Optimizes the maximum delay from clock to output pad, either for a specific clock or for an entire design

•INPAD_TO_OUTPAD

Optimizes the maximum delay from input pad to output pad throughout an entire design

•MAX_DELAY

Incorporates all previously mentioned constraints

These constraints affect the entire design. They apply only if no timing constraints are specified in the constraint file.

Define Global Optimization Goal globally with the -glob_opt command line option of the run command:

-glob_opt {allclocknets|offset_in_before|offset_out_after |inpad_to_outpad|max_delay}

Specify Global Optimization Goal globally in Project Navigator > Process

Properties > Synthesis Options > Global Optimization Goal.

Global Optimization Goal Domain Definitions

The possible domains are shown in the following schematic.

•ALLCLOCKNETS (register to register)

Identifies, by default, all paths from register to register on the same clock for all clocks in a design. To take inter-clock domain delays into account, set “Cross Clock Analysis (–cross_clock_analysis)” to yes.

•OFFSET_IN_BEFORE (inpad to register)

Identifies all paths from all primary input ports to either all sequential elements or the sequential elements driven by the given clock signal name.

•OFFSET_OUT_AFTER (register to outpad)

Similar to the previous constraint, but sets the constraint from the sequential elements to all primary output ports.

•INPAD_TO_OUTPAD (inpad to outpad)

Sets a maximum combinational path constraint.

10.1