Power Reduction (POWER)

Power Reduction (POWER) instructs XST to optimize the design to consume as little power as possible. Macro processing decisions are made to implement functions in a manner than uses minimal power. Although Power Reduction is allowed in both AREA and SPEED modes, it may negatively impact the final overall area and speed of the design.

In the current release, power optimization done by XST is dedicated to DSP48 and BRAM blocks.

XST supports two BRAM optimization methods :

•Method One does not significantly impact area and speed. Method One is used by default when power optimization is enabled.

•Method Two saves more power, but may significantly impact area and speed.

Both methods can be controlled by using the “RAM Style (RAM_STYLE)” constraint with block_power1 for Method One and block_power2 for Method Two.

In some situations, XST may issue an HDL Advisor message giving you tips on how to improve your design. For example, if XST detects that Read First mode is used for BRAM, XST recommends that you use Write First or No Change modes.

Power Reduction Architecture Support

Power Reduction applies to Virtex-4 and Virtex-5 devices only. Power Reduction does not apply to CPLD devices.

Power Reduction Applicable Elements

Apply Power Reduction to:

•A component or entity (VHDL)

•A model or label (instance) (Verilog)

•A model or INST (in model) (XCF)

•The entire design (XST command line)

Power Reduction Propagation Rules

Power Reduction applies to the entity, module, or signal to which it is attached.

Power Reduction Syntax Examples

Following are syntax examples using Power Reduction with particular tools or methods. If a tool or method is not listed, Power Reduction may not be used with it.

Power Reduction VHDL Syntax Example

Before using Power Reduction, declare it with the following syntax:

attribute power: string;

After declaring Power Reduction, specify the VHDL constraint:

attribute power of {component name|entity_name} : {component|entity} is "{yes|no}";

The default is no.

Power Reduction Verilog Syntax Example

Place Power Reduction immediately before the module declaration or instantiation:

(* power = "{yes|no}" *)

The default is no.

Power Reduction XCF Syntax Example

MODEL "entity_name" power = {yes|no|true|false};

The default is false.

Power Reduction XST Command Line Syntax Example

Define Power Reduction globally with the -power command line option of the run command:

-power {yes|no}

The default is no.

Power Reduction Project Navigator Syntax Example

Specify Power Reduction globally in Project Navigator > Process Properties > Synthesis Options > Power Reduction.

Read Cores (READ_CORES)

Use Read Cores (READ_CORES) to enable or disable the ability of XST to read Electronic Data Interchange Format (EDIF) or NGC core files for timing estimation and device utilization control. By reading a specific core, XST is better able to optimize logic around the core, since it sees how the logic is connected. However, in some cases the Read Cores operation must be disabled in XST in order to obtain the desired results. For example, the PCI core must not be visible to XST, since the logic directly connected to the PCI core must be optimized differently as compared to other cores. Read Cores allows you to enable or disable read operations on a core by core basis.

For more information, see “Cores Processing.”

Read Cores has three possible values:

•no (false)

Disables cores processing

•yes (true)

Enables cores processing, but maintains the core as a black box and does not further incorporate the core into the design

•optimize

Enables cores processing, and merges the core’s netlist into the overall design. This value is available through the XST command line mode only.

10.1

Read Cores Architecture Support

Read Cores applies to all FPGA devices. Read Cores does not apply to CPLD devices.

Read Cores Applicable Elements

Since Read Cores can be used with “BoxType (BOX_TYPE)” the set of objects on which the both constraints can be applied must be the same.

Apply Read Cores to:

•A component or entity (VHDL)

•A model or label (instance) (Verilog)

•A model or INST (in model) (XCF)

•The entire design (XST command line)

If Read Cores is applied to at least a single instance of a block, then Read Cores is applied to all other instances of this block for the entire design.

Read Cores Propagation Rules

Not applicable

Read Cores Syntax Examples

Following are syntax examples using Read Cores with particular tools or methods. If a tool or method is not listed, Read Cores may not be used with it.

Read Cores VHDL Syntax Example

Before using Read Cores, declare it with the following syntax:

attribute read_cores: string;

After declaring Read Cores, specify the VHDL constraint:

attribute read_cores of {component_name|entity_name} : {component|entity} is "{yes|no|optimize}";

The default is yes.

Read Cores Verilog Syntax Example

Place Read Cores immediately before the module declaration or instantiation:

(* read_cores = "{yes|no|optimize}" *)

The default is yes.

Read Cores XCF Syntax Example One

MODEL "entity_name" read_cores = {yes|no|true|false|optimize};

Read Cores XCF Syntax Example Two

BEGIN MODEL "entity_name"

INST "instance_name" read_cores = {yes|no|true|false|optimize};

END;

The default is yes.

Read Cores XST Command Line Syntax Example

-read_cores {yes|no|optimize}

Read Cores Project Navigator Syntax Example

Define Read Cores globally in Project Navigator > Process Properties >

Synthesis Options > Read Cores.

The optimize option is not available in Project Navigator.

Resynthesize (RESYNTHESIZE)

Resynthesize (RESYNTHESIZE) forces or prevents resynthesis of groups created by the “Incremental Synthesis (INCREMENTAL_SYNTHESIS)” constraint.

Resynthesize values are:

•yes

•no

•true (XCF only)

•false (XCF only)

There is no global option.

Resynthesize Architecture Support

Resynthesize applies to all FPGA devices. Resynthesize does not apply to CPLD devices.

Resynthesize Applicable Elements

Resynthesize applies to design elements only.

Resynthesize Propagation Rules

Resynthesize applies to the entity or module to which it is attached.

Resynthesize Syntax Examples

Following are syntax examples using Resynthesize with particular tools or methods. If a tool or method is not listed, Resynthesize may not be used with it.

Resynthesize VHDL Syntax Example

Before using Resynthesize declare it with the following syntax:

attribute resynthesize: string;

After declaring Resynthesize, specify the VHDL constraint:

attribute resynthesize of entity_name: entity is "{yes|no}";

Resynthesize Verilog Syntax Example

Place Resynthesize immediately before the module declaration or instantiation:

(* resynthesize = "{yes|no}" *)

Resynthesize XCF Syntax Example

MODEL "entity_name" resynthesize={yes|no};

10.1