Specifying INIT and RLOC Values for a Flip-Flop Coding Examples

This section gives the following Specifying INIT and RLOC Values for a Flip-Flop coding examples:

•“Specifying INIT and RLOC Values for a Flip-Flop VHDL Coding Example”

•“Specifying INIT and RLOC Values for a Flip-Flop Verilog Coding Example”

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip

To infer a register as shown in “” and “Specifying INIT Value for a Flip-Flop Verilog Coding Example,” and place it in a specific location of a chip, attach an “RLOC” constraint to the tmp signal as shown in the following coding examples.

XST propagates it to the final netlist. This feature is supported for registers, and also for inferred block RAM if it can be implemented on a single block RAM primitive.

Specifying INIT and RLOC Values for a Flip-Flop VHDL Coding Example

--

-- Specification on an INIT and RLOC values for a flip-flop, described at RTL level

--

library ieee;

use ieee.std_logic_1164.all;

entity inits_rlocs_3 is

port (CLK : in std_logic;

DI : in std_logic_vector(3 downto 0); DO : out std_logic_vector(3 downto 0));

end inits_rlocs_3;

architecture beh of inits_rlocs_3 is

signal tmp: std_logic_vector(3 downto 0):="1011";

attribute RLOC: string;

attribute RLOC of tmp: signal is "X3Y0 X2Y0 X1Y0 X0Y0"; begin

process (CLK) begin

if (clk'event and clk='1') then tmp <= DI;

end if; end process;

DO <= tmp;

end beh;

Specifying INIT and RLOC Values for a Flip-Flop Verilog Coding Example

//

//Specification on an INIT and RLOC values for a flip-flop,

//described at RTL level

//

module v_inits_rlocs_3 (clk, di, do);