information, see “PERIOD Specifications on CLKDLLs and DCMs” in the Xilinx

Constraints Guide.

A TNM_NET is a property that you normally use in conjunction with a Hardware Description Language (HDL) design to tag a specific net. All downstream synchronous elements and pads tagged with the TNM_NET identifier are considered a group. For more information, see “TNM_NET”” in the Xilinx Constraints Guide.

Timing Name on a Net XCF Syntax Example

NET netname TNM_NET = [predefined_group:] identifier;

Timegroup (TIMEGRP)

Timegroup (TIMEGRP) is a basic grouping constraint. In addition to naming groups using the TNM identifier, you can also define groups in terms of other groups. You can create a group that is a combination of existing groups by defining a TIMEGRP constraint.

You can place TIMEGRP constraints in a constraints file (XST Constraint File (XCF) or Netlist Constraints File (NCF). You can use TIMEGRP attributes to create groups using the following methods.

•Combining multiple groups into one

•Defining flip-flop subgroups by clock sense

For more information, see “TIMEGRP” in the Xilinx Constraints Guide.

Timegroup XCF Syntax Example

TIMEGRP newgroup = existing_grp1 existing_grp2 [existing_grp3 ...];

Timing Ignore (TIG)

Timing Ignore (TIG) causes all paths going through a specific net to be ignored for timing analyses and optimization purposes. Timing Ignore can be applied to the name of the signal affected. For more information, see “TIG” in the Xilinx Constraints Guide.

Timing Ignore XCF Syntax Example

NET net_name TIG;

XST Implementation Constraints

This section discusses XST implementation constraints. For more information, see the

Xilinx Constraints Guide. This section includes:

•“About Implementation Constraints”

•“Implementation Constraints Syntax Examples”

•“RLOC”

•“NOREDUCE”

•“PWR_MODE”

About Implementation Constraints

Implementation constraints control placement and routing. They are not directly used by XST, but are simply propagated and made available to the implementation tools. The object to which an implementation constraint is attached is preserved.

A binary equivalent of the implementation constraints is written to the NGC file. Since the file is binary, you cannot edit implementation constraints in the NGC file.

Alternatively, you can code implementation constraints in the XST Constraint File (XCF) using the syntaxes shown in “Implementation Constraints Syntax Examples.”

Implementation Constraints Syntax Examples

This section gives the following Implementation Constraints coding examples:

•“Implementation Constraints XCF Syntax Examples”

•“Implementation Constraints VHDL Syntax Examples”

•“Implementation Constraints Verilog Syntax Examples”

Implementation Constraints XCF Syntax Examples

To apply an implementation constraint to an entire entity, use either of the following XST Constraint File (XCF) syntaxes:

MODEL EntityName PropertyName;

MODEL EntityName PropertyName=PropertyValue;

To apply an implementation constraint to specific instances, nets, or pins within an entity, use either of the following syntaxes:

BEGIN MODEL EntityName

{NET|INST|PIN} {NetName|InstName|SigName} PropertyName;

END;

BEGIN MODEL EntityName

{NET|INST|PIN} {NetName|InstName|SigName} PropertyName=Propertyvalue;

END;

Implementation Constraints VHDL Syntax Examples

Specify implementation constraints in VHDL as follows:

attribute PropertyName of {NetName|InstName|PinName} : {signal|label} is "PropertyValue";

Implementation Constraints Verilog Syntax Examples

Specify implementation constraints in Verilog as follows:

// synthesis attribute PropertyName of {NetName|InstName|PinName} is "PropertyValue";

In Verilog-2001, where descriptions precede the signal, module, or instance to which they refer, specify implementation constraints as follows:

(* PropertyName="PropertyValue" *)

10.1

RLOC

RLOC applies to all FPGA devices. RLOC does not apply to CPLD devices.

Use RLOC to indicate the placement of a design element on the FPGA die relative to other elements. Assuming an SRL16 instance of name srl1 to be placed at location R9C0.S0, you may specify the following in the Verilog code:

// synthesis attribute RLOC of srl1 : "R9C0.S0";

You may specify the same attribute in the XST Constraint File (XCF) as follows:

BEGIN MODEL ENTNAME

INST sr11 RLOC=R9C0.SO;

END;

The binary equivalent of the following line is written to the output NGC file:

INST srl1 RLOC=R9C0.S0;

For more information, see “RLOC” in the Xilinx Constraints Guide.

NOREDUCE

NOREDUCE applies to all CPLD devices. NOREDUCE does not apply to FPGA devices.

NOREDUCE prevents the optimization of the boolean equation generating a given signal. Assuming a local signal is assigned the arbitrary function below, and NOREDUCE attached to the signal s:

signal s : std_logic;

attribute NOREDUCE : boolean;

attribute NOREDUCE of s : signal is "true";

...

s <= a or (a and b);

Specify NOREDUCE in the XST Constraint File (XCF) as follows:

BEGIN MODEL ENTNAME

NET s NOREDUCE;

NET s KEEP;

END;

XST writes the following statements to the NGC file:

NET s NOREDUCE;

NET s KEEP;

For more information, see “NOREDUCE” in the Xilinx Constraints Guide.