Sequential Complex Multipliers HDL Coding Techniques

Unsigned 8x4-Bit Multiplier VHDL Coding Example

--

-- Unsigned 8x4-bit Multiplier

--

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity multipliers_1 is

port(A : in std_logic_vector(7 downto 0); B : in std_logic_vector(3 downto 0);

RES : out std_logic_vector(11 downto 0)); end multipliers_1;

architecture beh of multipliers_1 is begin

RES <= A * B; end beh;

Unsigned 8x4-Bit Multiplier Verilog Coding Example

//

// Unsigned 8x4-bit Multiplier

//

module v_multipliers_1(A, B, RES); input [7:0] A;

input [3:0] B; output [11:0] RES;

assign RES = A * B; endmodule

Sequential Complex Multipliers HDL Coding Techniques

This section discusses Sequential Complex Multipliers HDL Coding Techniques, and includes:

•“About Sequential Complex Multipliers”

•“Sequential Complex Multipliers Log File”

•“Sequential Complex Multipliers Related Constraints”

•“Sequential Complex Multipliers Coding Examples”

About Sequential Complex Multipliers

A sequential complex multiplier is a complex multiplier that requires four cycles to make a complete multiplication by accumulating intermediate results. From the implementation point of view, it requires one DSP block.

Multiplying two complex numbers A and B requires four cycles.

The first two first cycles compute:

Res_real = A_real * B_real - A_imag * B_imag

10.1

The second two cycles compute:

Res_imag = A_real * B_imag + A_imag * B_real

While several templates could be used to describe the above functionality, XST does not support using enum or integer types to describe the different DSP modes and store the enum values. Instead, Xilinx recommends a very regular template to ease XST inferencing. This general accumulator template allows XST to inference a single DSP to perform the following operations:

•Load: P <= Value

•Load: P <= -Value

•Accumulate: P <= P + Value

•Accumulate: P <= P - Value

This template works with two control signals, load and addsub, that perform the above four operations when combined.

Sequential Complex Multipliers Log File

•None

Sequential Complex Multipliers Related Constraints

•None

Sequential Complex Multipliers Coding Examples

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

•“Signed 18x18-bit Sequential Complex Multiplier”

Signed 18x18-bit Sequential Complex Multiplier

This section discusses Signed 18x18-bit Sequential Complex Multiplier, and includes:

•“Signed 18x18-bit Sequential Complex Multiplier Pin Descriptions”

•“Signed 18x18-bit Sequential Complex Multiplier VHDL Coding Example”

•“Signed 18x18-bit Sequential Complex Multiplier Verilog Coding Example”

Table 2-55: Signed 18x18-bit Sequential Complex Multiplier Pin Descriptions

Signed 18x18-bit Sequential Complex Multiplier VHDL Coding Example

--

-- Sequential Complex Multiplier

--

library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all;

end multipliers_8;

architecture beh of multipliers_8 is

constant P_WIDTH: integer:=A_WIDTH+B_WIDTH;

signal oper_load0: std_logic:=’0’; signal oper_addsub0: std_logic:=’0’;

signal p1: signed(P_WIDTH-1 downto 0):=(others=>’0’); signal oper_load1: std_logic:=’0’;

signal oper_addsub1: std_logic:=’0’;

signal res0: signed(RES_WIDTH-1 downto 0); begin

process (clk)

variable acc: signed(RES_WIDTH-1 downto 0); begin

if rising_edge(clk) then oper_load0 <= Oper_Load; oper_addsub0 <= Oper_AddSub;

p1 <= A*B;

oper_load1 <= oper_load0; oper_addsub1 <= oper_addsub0;

if (oper_load1=’1’) then acc := res0;

else

acc := (others=>’0’);

10.1

end if;

if (oper_addsub1=’1’) then res0 <= acc-p1;

else

res0 <= acc+p1; end if;

end if; end process;

RES <= res0;

end architecture;

Signed 18x18-bit Sequential Complex Multiplier Verilog Coding Example

module v_multipliers_8(CLK,A,B,Oper_Load,Oper_AddSub, RES);

reg signed [P_WIDTH-1:0] p1 = 0; reg oper_load1 = 0;

reg oper_addsub1 = 0;

reg signed [RES_WIDTH-1:0] res0 = 0; reg signed [RES_WIDTH-1:0] acc;

always @(posedge CLK) begin

oper_load0 <= Oper_Load; oper_addsub0 <= Oper_AddSub;

p1 <= A*B;

oper_load1 <= oper_load0; oper_addsub1 <= oper_addsub0;

if (oper_load1==1’b1) acc = res0;

else

acc = 0;