Pipelined Multipliers HDL Coding Techniques

if (oper_addsub1==1’b1) res0 <= acc-p1;

else

res0 <= acc+p1;

end

assign RES = res0;

endmodule

Pipelined Multipliers HDL Coding Techniques

This section discusses Pipelined Multipliers HDL Coding Techniques, and includes:

•“About Pipelined Multipliers”

•“Pipelined Multipliers Log File”

•“Pipelined Multipliers Related Constraints”

•“Pipelined Multipliers Coding Examples”

About Pipelined Multipliers

To increase the speed of designs with large multipliers, XST can infer pipelined multipliers. By interspersing registers between the stages of large multipliers, pipelining can significantly increase the overall frequency of your design. The effect of pipelining is similar to flip-flop retiming which is described in “Flip-Flop Retiming.”

To insert pipeline stages, describe the necessary registers in your HDL code and place them after any multipliers, then set the “Multiplier Style (MULT_STYLE)” constraint to pipe_lut. If the target is a Virtex-4 or Virtex-5 device, and implementation of a multiplier requires multiple DSP48 blocks, XST can pipeline this implementation as well. Set “Multiplier Style (MULT_STYLE)” for this instance to pipe_block.

When XST detects valid registers for pipelining and “Multiplier Style (MULT_STYLE)” is set to pipe_lut or pipe_block, XST uses the maximum number of available registers to reach the maximum multiplier speed. XST automatically calculates the maximum number of registers for each multiplier to obtain the best frequency.

If you have not specified sufficient register stages, and “Multiplier Style (MULT_STYLE)” is coded directly on a signal, the XST HDL Advisor advises you to specify the optimum number of register stages. XST does this during the Advanced HDL Synthesis step. If the number of registers placed after the multiplier exceeds the maximum required, and shift register extraction is activated, then XST implements the unused stages as shift registers.

XST has the following limitations:

•XST cannot pipeline hardware Multipliers (implementation using MULT18X18S resource).

•XST cannot pipeline Multipliers if registers contain asynch set/reset or synch reset signals. XST can pipeline if registers contain synch reset signals.

10.1

Pipelined Multipliers Log File

Following is a Pipelined Multipliers log file.

====================================================================

* HDL Synthesis *

====================================================================

Synthesizing Unit <multipliers_2>.

Related source file is "multipliers_2.vhd".

Unit <multipliers_2> synthesized.

...

====================================================================

* Advanced HDL Synthesis *

====================================================================

Synthesizing (advanced) Unit <multipliers_2>.

Found pipelined multiplier on signal <mult_res>:

- 4 pipeline level(s) found in a register connected to the multiplier macro output.

Pushing register(s) into the multiplier macro. INFO:Xst - HDL ADVISOR - You can improve the performance of the multiplier Mmult_mult_res by adding 1 register level(s).

Unit <multipliers_2> synthesized (advanced).

====================================================================

HDL Synthesis Report

====================================================================

Pipelined Multipliers Related Constraints

•“Use DSP48 (USE_DSP48)”

•“DSP Utilization Ratio (DSP_UTILIZATION_RATIO)”

•“Keep (KEEP)”

•“Multiplier Style (MULT_STYLE)”

Pipelined Multipliers Coding Examples

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

•“Pipelined Multiplier (Outside, Single)”

•“Pipelined Multiplier (Inside, Single)”

•“Pipelined Multiplier (Outside, Shift)”

Pipelined Multiplier (Outside, Single)

This section discusses Pipelined Multiplier (Outside, Single), and includes:

•“Pipelined Multiplier (Outside, Single) Diagram”

•“Pipelined Multiplier (Outside, Single) Pin Descriptions”

•“Pipelined Multiplier (Outside, Single) VHDL Coding Example”

•“Pipelined Multiplier (Outside, Single) Verilog Coding Example”

Figure 2-46: Pipelined Multiplier (Outside, Single) Diagram

Table 2-56: Pipelined Multiplier (Outside, Single) Pin Descriptions

Pipelined Multiplier (Outside, Single) VHDL Coding Example

--

--Pipelined multiplier

--The multiplication operation placed outside the

--process block and the pipeline stages represented

--as single registers.

--

library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity multipliers_2 is generic(A_port_size : integer := 18;

10.1

B_port_size : integer := 18); port(clk : in std_logic;

A : in unsigned (A_port_size-1 downto 0); B : in unsigned (B_port_size-1 downto 0);

MULT : out unsigned ( (A_port_size+B_port_size-1) downto 0));

attribute mult_style: string;

attribute mult_style of multipliers_2: entity is "pipe_lut";

end multipliers_2;

architecture beh of multipliers_2 is

signal a_in, b_in : unsigned (A_port_size-1 downto 0);

signal mult_res : unsigned ( (A_port_size+B_port_size-1) downto 0); signal pipe_1,

pipe_2,

pipe_3 : unsigned ((A_port_size+B_port_size-1) downto 0);

begin

mult_res <= a_in * b_in;

process (clk) begin

if (clk'event and clk='1') then a_in <= A; b_in <= B; pipe_1 <= mult_res;

pipe_2 <= pipe_1; pipe_3 <= pipe_2; MULT <= pipe_3;

end if; end process;

end beh;

Pipelined Multiplier (Outside, Single) Verilog Coding Example

//

//Pipelined multiplier

//The multiplication operation placed outside the

//always block and the pipeline stages represented

//as single registers.

//

(*mult_style="pipe_lut"*)

module v_multipliers_2(clk, A, B, MULT);

input clk; input [17:0] A; input [17:0] B;

output [35:0] MULT; reg [35:0] MULT;

reg [17:0] a_in, b_in; wire [35:0] mult_res;

reg [35:0] pipe_1, pipe_2, pipe_3;

assign mult_res = a_in * b_in;

always @(posedge clk)

begin

a_in <= A; b_in <= B; pipe_1 <= mult_res; pipe_2 <= pipe_1; pipe_3 <= pipe_2; MULT <= pipe_3;

end endmodule

Pipelined Multiplier (Inside, Single)

This section discusses Pipelined Multiplier (Inside, Single), and includes:

•“Pipelined Multiplier (Inside, Single) Pin Descriptions”

•“Pipelined Multiplier (Inside, Single) VHDL Coding Example”

•“Pipelined Multiplier (Inside, Single) Verilog Coding Example”

Table 2-57: Pipelined Multiplier (Inside, Single) Pin Descriptions

Pipelined Multiplier (Inside, Single) VHDL Coding Example

--

--Pipelined multiplier

--The multiplication operation placed inside the

--process block and the pipeline stages represented

--as single registers.

--

library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity multipliers_3 is generic(A_port_size: integer := 18;

B_port_size: integer := 18); port(clk : in std_logic;

A : in unsigned (A_port_size-1 downto 0); B : in unsigned (B_port_size-1 downto 0);

MULT : out unsigned ((A_port_size+B_port_size-1) downto 0));

attribute mult_style: string;

attribute mult_style of multipliers_3: entity is "pipe_lut";

end multipliers_3;

architecture beh of multipliers_3 is

signal a_in, b_in : unsigned (A_port_size-1 downto 0);

signal mult_res : unsigned ((A_port_size+B_port_size-1) downto 0); signal pipe_2,

pipe_3 : unsigned ((A_port_size+B_port_size-1) downto 0);

10.1

begin

process (clk) begin

if (clk'event and clk='1') then a_in <= A; b_in <= B; mult_res <= a_in * b_in; pipe_2 <= mult_res;

pipe_3 <= pipe_2; MULT <= pipe_3;

end if; end process;

end beh;

Pipelined Multiplier (Inside, Single) Verilog Coding Example

//

//Pipelined multiplier

//The multiplication operation placed inside the

//process block and the pipeline stages are represented

//as single registers.

//

(*mult_style="pipe_lut"*)

module v_multipliers_3(clk, A, B, MULT);

input clk; input [17:0] A; input [17:0] B;

output [35:0] MULT; reg [35:0] MULT;

reg [17:0] a_in, b_in; reg [35:0] mult_res;

reg [35:0] pipe_2, pipe_3;

always @(posedge clk) begin

a_in <= A; b_in <= B; mult_res <= a_in * b_in; pipe_2 <= mult_res; pipe_3 <= pipe_2;

MULT <= pipe_3;

end endmodule

Pipelined Multiplier (Outside, Shift)

This section discusses Pipelined Multiplier (Outside, Shift), and includes:

•“Pipelined Multiplier (Outside, Shift) Pin Descriptions”

•“Pipelined Multiplier (Outside, Shift) VHDL Coding Example”

•“Pipelined Multiplier (Outside, Shift) Verilog Coding Example”

Table 2-58: Pipelined Multiplier (Outside, Shift) Pin Descriptions

Pipelined Multiplier (Outside, Shift) VHDL Coding Example

--

--Pipelined multiplier

--The multiplication operation placed outside the

--process block and the pipeline stages represented

--as shift registers.

--

library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity multipliers_4 is generic(A_port_size: integer := 18;

B_port_size: integer := 18); port(clk : in std_logic;

A : in unsigned (A_port_size-1 downto 0); B : in unsigned (B_port_size-1 downto 0);

MULT : out unsigned ( (A_port_size+B_port_size-1) downto 0));

attribute mult_style: string;

attribute mult_style of multipliers_4: entity is "pipe_lut";

end multipliers_4;

architecture beh of multipliers_4 is

signal a_in, b_in : unsigned (A_port_size-1 downto 0);

signal mult_res : unsigned ((A_port_size+B_port_size-1) downto 0);

type pipe_reg_type is array (2 downto 0) of unsigned ((A_port_size+B_port_size-1) downto 0);

signal pipe_regs : pipe_reg_type;

begin

mult_res <= a_in * b_in;

process (clk) begin

if (clk'event and clk='1') then a_in <= A; b_in <= B;

10.1

pipe_regs <= mult_res & pipe_regs(2 downto 1); MULT <= pipe_regs(0);

end if; end process;

end beh;

Pipelined Multiplier (Outside, Shift) Verilog Coding Example

//

//Pipelined multiplier

//The multiplication operation placed outside the

//always block and the pipeline stages represented

//as shift registers.

//

(*mult_style="pipe_lut"*)

module v_multipliers_4(clk, A, B, MULT);

input clk; input [17:0] A; input [17:0] B;

output [35:0] MULT; reg [35:0] MULT;

reg [17:0] a_in, b_in; wire [35:0] mult_res;

reg [35:0] pipe_regs [2:0]; integer i;

assign mult_res = a_in * b_in;

always @(posedge clk) begin

a_in <= A; b_in <= B;

pipe_regs[2] <= mult_res;

for (i=0; i<=1; i=i+1) pipe_regs[i] <= pipe_regs[i+1];

MULT <= pipe_regs[0];

end

endmodule