Mapping Logic Onto Block RAM

To deliver the best performance, XST by default tries to infer and implement the maximum macro configuration, including as many registers in the DSP48 as possible. Use “Keep (KEEP)” to shape a macro in a specific way. For example, if your design has a multiplier with two register levels on each input, place “Keep (KEEP)” constraints on the outputs of these registers to exclude the first register stage from the DSP48.

DSP48 blocks do not support registers with Asynchronous Set/Reset signals. Since such registers cannot be absorbed by DSP48, this may lead to sub-optimal performance. The “Asynchronous to Synchronous (ASYNC_TO_SYNC)” constraint allows you to replace Asynchronous Set/Reset signals with Synchronous signals throughout the entire design. This allows absorption of registers by DSP48, thereby improving quality of results.

Replacing Asynchronous Set/Reset signals by Synchronous signals makes the generated NGC netlist NOT equivalent to the initial RTL description. You must ensure that the synthesized design satisfies the initial specification. For more information, see“Asynchronous to Synchronous (ASYNC_TO_SYNC)”

For more information on individual macro processing, see “XST HDL Coding

Techniques.”

If your design contains several interconnected macros, where each macro can be implemented on DSP48, XST attempts to interconnect DSP48 blocks using fast BCIN/BCOUT and PCIN/PCOUT connections. Such situations are typical in filter and complex multiplier descriptions.

XST can build complex DSP macros and DSP48 chains across the hierarchy when the “Keep Hierarchy (KEEP_HIERARCHY)” command line option is set to no. This is the default in ISE ™.

Mapping Logic Onto Block RAM

This section discusses Mapping Logic Onto Block RAM, and includes:

•“About Mapping Logic Onto Block RAM”

•“Mapping Logic Onto Block RAM Log Files”

•“Mapping Logic Onto Block RAM Coding Examples”

About Mapping Logic Onto Block RAM

If your design does not fit into the target device, you can place some of the design logic into unused block RAM:

1.Put the part of the RTL description to be placed into block RAM in a separate hierarchical block.

2.Attach a “Map Logic on BRAM (BRAM_MAP)” constraint to the separate hierarchical block, either directly in HDL code, or in the XST Constraint File (XCF).

XST cannot automatically decide which logic can be placed in block RAM.

Logic placed into a separate block must satisfy the following criteria:

•All outputs are registered.

•The block contains only one level of registers, which are output registers.

•All output registers have the same control signals.

•The output registers have a Synchronous Reset signal.

10.1

•The block does not contain multisources or tristate busses.

•“Keep (KEEP)” is not allowed on intermediate signals.

XST attempts to map the logic onto block RAM during the Advanced Synthesis step. If any of the listed requirements are not satisfied, XST does not map the logic onto block RAM, and issues a warning. If the logic cannot be placed in a single block RAM primitive, XST spreads it over several block RAMs.

Mapping Logic Onto Block RAM Log Files

This section contains examples of Mapping Logic Onto Block RAM Log Files:

•“Mapping Logic Onto Block RAM Log Files Example One”

•“Mapping Logic Onto Block RAM Log Files Example Two”

Mapping Logic Onto Block RAM Log Files Example One

...

====================================================================

* HDL Synthesis *

====================================================================

Synthesizing Unit <logic_bram_1>.

Related source file is "bram_map_1.vhd".

Found 4-bit register for signal <RES>.

Found 4-bit adder for signal <$n0001> created at line 29.

Summary:

Unit <logic_bram_1> synthesized.

===================================================================

* Advanced HDL Synthesis *

===================================================================

...

Entity <logic_bram_1> mapped on BRAM.

...

===================================================================

HDL Synthesis Report

===================================================================

...

Mapping Logic Onto Block RAM Log Files Example Two

...

===================================================================

* Advanced HDL Synthesis *

===================================================================

...

INFO:Xst:1789 - Unable to map block <no_logic_bram> on BRAM. Output FF <RES> must have a synchronous reset.

Mapping Logic Onto Block RAM Coding Examples

This section gives the following Mapping Logic Onto Block RAM coding examples:

•“8-Bit Adders With Constant in a Single Block Ram Primitive VHDL Coding Example”

•“8-Bit Adders With Constant in a Single Block Ram Primitive Verilog Coding Example”

•“Asynchronous Reset VHDL Coding Example”

•“Asynchronous Reset Verilog Coding Example”

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

8-Bit Adders With Constant in a Single Block Ram Primitive VHDL Coding Example

--

--The following example places 8-bit adders with

--constant in a single block RAM primitive

--

library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity logic_bram_1 is

port (clk, rst : in std_logic;

A,B : in unsigned (3 downto 0); RES : out unsigned (3 downto 0));

attribute bram_map: string;

attribute bram_map of logic_bram_1: entity is "yes";

end logic_bram_1;

architecture beh of logic_bram_1 is begin

process (clk) begin

if (clk'event and clk='1') then if (rst = '1') then

RES <= "0000";

else

RES <= A + B + "0001"; end if;

end if; end process;

end beh;

8-Bit Adders With Constant in a Single Block Ram Primitive Verilog Coding Example

//

//The following example places 8-bit adders with

//constant in a single block RAM primitive

//

(* bram_map="yes" *)

10.1

module v_logic_bram_1 (clk, rst, A, B, RES);

RES <= 4'b0000; else

RES <= A + B + 8'b0001;

end

endmodule

Asynchronous Reset VHDL Coding Example

--

--In the following example, an asynchronous reset is used and

--so, the logic is not mapped onto block RAM

--

library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all;

entity logic_bram_2 is

port (clk, rst : in std_logic;

attribute bram_map : string;

attribute bram_map of logic_bram_2 : entity is "yes";

end logic_bram_2;

architecture beh of logic_bram_2 is begin

process (clk, rst) begin

if (rst='1') then RES <= "0000";

elsif (clk'event and clk='1') then RES <= A + B + "0001";

end if; end process;

end beh;

Asynchronous Reset Verilog Coding Example

//

//In the following example, an asynchronous reset is used and

//so, the logic is not mapped onto block RAM

//

(* bram_map="yes" *)