RAMs and ROMs HDL Coding Techniques

Resource Sharing VHDL Coding Example

--

-- Resource Sharing

--

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity resource_sharing_1 is

end resource_sharing_1;

architecture archi of resource_sharing_1 is begin

RES <= A + B when OPER='0' else A - C;

end archi;

Resource Sharing Verilog Coding Example

//

// Resource Sharing

//

module v_resource_sharing_1 (A, B, C, OPER, RES); input [7:0] A, B, C;

input OPER; output [7:0] RES; wire [7:0] RES;

assign RES = !OPER ? A + B : A - C;

endmodule

RAMs and ROMs HDL Coding Techniques

This section discusses RAMs and ROMs HDL Coding Techniques, and includes:

•“About RAMs and ROMs”

•“RAMs and ROMs Log File”

•“RAMs and ROMs Related Constraints”

•“RAMs and ROMs Coding Examples”

•“Initializing RAM Coding Examples”

About RAMs and ROMs

If you do not want to instantiate RAM primitives to keep your HDL code architecture independent, use XST automatic RAM recognition. XST can infer distributed as well as block RAM. It covers the following characteristics, offered by these RAM types:

10.1

•Synchronous write

•Write enable

•RAM enable

•Asynchronous or synchronous read

•Reset of the data output latches

•Data output reset

•Single, dual or multiple-port read

•Single-port/Dual-port write

•Parity bits (Supported for all FPGA devices except Virtex, Virtex-E, Spartan-II, and Spartan-IIE)

•Block Ram with Byte-Wide Write Enable

•Simple dual-port BRAM

XST does not support RAMs and ROMs with negative addresses.

The type of inferred RAM depends on its description.

•RAM descriptions with an asynchronous read generate a distributed RAM macro.

•RAM descriptions with a synchronous read generate a block RAM macro. In some cases, a block RAM macro can actually be implemented with distributed RAM. The decision on the actual RAM implementation is done by the macro generator.

If a given template can be implemented using Block and Distributed RAM, XST implements BLOCK ones. Use the “RAM Style (RAM_STYLE)” constraint to control RAM implementation and select a desirable RAM type. For more information, see “XST Design Constraints.”

The following block RAM features are not yet supported:

•Parity bits (Virtex, Virtex-E, Spartan-II, and Spartan-IIE are not supported)

•Different aspect ratios on each port

•Simple dual-port distributed RAMs

•Quad-port distributed RAMs

XST uses speed-oriented implementation to implement RAMs on BRAM resources. This gives good results for speed, but may require more BRAM resources than area-oriented implementation. XST does not support area-oriented BRAM implementation. Xilinx recommends Core Generator for area-oriented implementation.

For more information on RAM implementation, see “XST FPGA Optimization.”

XST can implement Finite State Machines (see “Finite State Machines (FSMs) HDL Coding Techniques”) and map general logic (see “Mapping Logic Onto Block RAM”) on block RAMs.

XST automatically controls BRAM resources on the target device. “BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO)” allows you to specify the number of BRAM blocks that XST must not exceed during synthesis.

BRAM management goes through the following steps.

•To achieve better design speed, XST implements small RAMs and ROMs using distributed resources. RAMs and ROMs are considered small if their sizes follow the rules shown in Table 2-65, “Rules for Small RAMs and ROMs.”

Table 2-65: Rules for Small RAMs and ROMs

Use “RAM Style (RAM_STYLE)” and “ROM Style (ROM_STYLE)” to force implementation of small RAMs and ROMs on BRAM resources.

XST calculates the available BRAM resources for inference using the following formula:

Total_Number_of_Available_BRAMs - Number_of_Reserved_BRAMs

In this formula Total_Number_of_Available_BRAMs is the number of BRAMs specified by the “BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO)” constraint. By default it is 100%. The Number of Reserved_BRAMs encapsulates:

•The number of instantiated BRAMs in the HDL code from the UNISIM library

•The number of RAM which were forced to be implemented as BRAMs by the “RAM Style (RAM_STYLE)” and “ROM Style (ROM_STYLE)” constraints

•The number of BRAMs generated using BRAM mapping optimizations (BRAM_MAP).

Where there are available BRAM resources, XST implements the largest inferred RAMs and ROMs using BRAM, and the smallest on distributed resources.

If the Number_of_Reserved_BRAMs exceeds available resources, XST implements them as block RAMs, and all inferred RAMs are implemented on distributed memory.

As soon as this process is completed, XST can automatically pack two small single-port BRAMs in a single BRAM primitive. This optimization is controlled by the “Automatic BRAM Packing (AUTO_BRAM_PACKING)” constraint. It is disabled by default.

For more information, see “BRAM Utilization Ratio (BRAM_UTILIZATION_RATIO)” and “Automatic BRAM Packing (AUTO_BRAM_PACKING).”

RAMs and ROMs Log File

The XST log file reports the type and size of recognized RAM as well as complete information on its I/O ports. RAM recognition consists of two steps.

•During the HDL Synthesis step, XST recognizes the presence of the memory structure in the HDL code.

•During the Advanced HDL Synthesis step, XST decides how to implement a specific memory (that is, whether to use Block or Distributed memory resources).

=========================================================================

* HDL Synthesis *

=========================================================================

Synthesizing Unit <rams_16>.

Related source file is "rams_16.vhd".

Found 64x16-bit dual-port RAM <Mram_RAM> for signal <RAM>.

Found 16-bit register for signal <doa>.

Found 16-bit register for signal <dob>.

10.1

Summary:

inferred 1 RAM(s).

inferred 32 D-type flip-flop(s). Unit <rams_16> synthesized.

=========================================================================

HDL Synthesis Report

=========================================================================

=========================================================================

* Advanced HDL Synthesis *

=========================================================================

Synthesizing (advanced) Unit <rams_16>.

INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <doa> <dob>

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