Move Last Stage (MOVE_LAST_STAGE)

Move Last Stage (MOVE_LAST_STAGE) controls the retiming of registers with paths going to primary outputs. Both Move Last Stage and “Move First Stage (MOVE_FIRST_STAGE)” relate to Register Balancing.

Move Last Stage Architecture Support

Move Last Stage applies to all FPGA devices. Move Last Stage does not apply to CPLD devices.

Move Last Stage Applicable Elements

Move Last Stage applies to the following only:

•Entire design

•Single modules or entities

•Primary clock signal

Move Last Stage Propagation Rules

For Move Last Stage propagation rules, see “Move First Stage (MOVE_FIRST_STAGE).”

Move Last Stage Syntax Examples

Following are syntax examples using Move Last Stage with particular tools or methods. If a tool or method is not listed, Move Last Stage may not be used with it.

Move Last Stage Syntax Example

Before using Move Last Stage, declare it with the following syntax:

attribute move_last_stage : string;

After declaring Move Last Stage, specify the VHDL constraint:

attribute move_last_stage of {entity_name|signal_name}: {signal|entity} is "{yes|no}";

Move Last Stage Verilog Syntax Example

Place Move Last Stage immediately before the module or signal declaration:

(* move_last_stage = "{yes|no}" *)

Move Last Stage XCF Syntax Example One

MODEL "entity_name" move_last_stage={yes|no|true|false};

Move Last Stage XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "primary_clock_signal" move_last_stage={yes|no|true|false};

END;

Move Last Stage XST Command Line Syntax Example

Define Move Last Stage globally with the –move_last_stage command line option of the run command:

-move_last_stage {yes|no}

The default is yes.

Move Last Stage Project Navigator Syntax Example

Define Move Last Stage globally in Project Navigator > Process Properties > Xilinx-Specific Options > Move Last Stage.

Multiplier Style (MULT_STYLE)

Multiplier Style (MULT_STYLE) controls the way the macrogenerator implements the multiplier macros.

Multiplier Style values are:

•auto

For Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5 devices, the default is auto. XST looks for the best implementation for each considered macro.

•block

•pipe_block

The pipe_block option is used to pipeline DSP48 based multipliers. It is available for Virtex-4 and Virtex-5 devices only

•kcm

•csd

•lut

•pipe_lut

The pipe_lut option is for pipeline slice-based multipliers. The implementation style can be manually forced to use block multiplier or LUT resources in the following devices:

♦Virtex-II, Virtex-II Pro

♦Virtex-4, Virtex-5 devies

Multiplier Style Architecture Support

Multiplier Style applies to the following FPGA devices only:

•Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A D

•Virtex-II, Virtex-II Pro

•Virtex-4, Virtex-5

Multiplier Style does not apply to CPLD devices.

Multiplier Style Applicable Elements

Multiplier Style applies globally, or to a VHDL entity, a Verilog module, or signal.

Multiplier Style Propagation Rules

Multiplier Style applies to the entity, module, or signal to which it is attached.

10.1

Multiplier Style Syntax Examples

Following are syntax examples using Multiplier Style with particular tools or methods. If a tool or method is not listed, Multiplier Style may not be used with it.

Multiplier Style VHDL Syntax Example

Before using Multiplier Style, declare it with the following syntax:

attribute mult_style: string;

After declaring Multiplier Style, specify the VHDL constraint:

attribute mult_style of {signal_name|entity_name}: {signal|entity} is "{auto|block|pipe_block|kcm|csd|lut|pipe_lut}";

For the following devices, the default is lut:

•Virtex, Virtex-E

•Spartan-II, Spartan-IIE

For the following devices, the default is auto:

•Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A D

•Virtex-II, Virtex-II Pro

•Virtex-4, Virtex-5

Multiplier Style Verilog Syntax Example

Place Multiplier Style immediately before the module or signal declaration:

(* mult_style = "{auto|block|pipe_block|kcm|csd|lut|pipe_lut}" *)

For the following devices, the default is lut:

•Virtex, Virtex-E

•Spartan-II, Spartan-IIE

For the following devices, the default is auto:

•Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A D

•Virtex-II, Virtex-II Pro

•Virtex-4, Virtex-5

Multiplier Style XCF Syntax Example One

MODEL "entity_name" mult_style={auto|block|pipe_block|kcm|csd|lut|pipe_lut};

Multiplier Style XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" mult_style={auto|block|pipe_block|kcm|csd|lut|pipe_lut};

END;

Multiplier Style XST Command Line Syntax Example

Define Multiplier Style globally with the -mult_style command line option of the run command:

-mult_style {auto|block|pipe_block|kcm|csd|lut|pipe_lut}

For the following devices, the default is lut:

•Virtex, Virtex-E

•Spartan-II, Spartan-IIE

For the following devices, the default is auto:

•Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A D

•Virtex-II, Virtex-II Pro

•Virtex-4, Virtex-5

The -mult_style command line option is not supported for Virtex-4 or Virtex-5 devices. For those devices, use -use_dsp48.

Multiplier Style Project Navigator Syntax Example

Define Multiplier Style globally in Project Navigator > Process Properties > HDL Options > Multiplier Style.

Mux Style (MUX_STYLE)

Mux Style (MUX_STYLE) controls the way the macrogenerator implements the multiplexer macros.

Mux Style values are:

•auto (default)

•muxf

•muxcy

The default is auto. XST looks for the best implementation for each considered macro.

Table 5-5: Available Mux Style Implementation Styles

Mux Style Architecture Support

Mux Style applies to all FPGA devices. Mux Style does not apply to CPLD devices.

10.1