Equivalent Register Removal Syntax Examples

Following are syntax examples using Equivalent Register Removal with particular tools or methods. If a tool or method is not listed, Equivalent Register Removal may not be used with it.

Equivalent Register Removal VHDL Syntax Example

Before using Equivalent Register Removal, declare it with the following syntax:

attribute equivalent_register_removal: string;

After declaring Equivalent Register Removal, specify the VHDL constraint:

attribute equivalent_register_removal of {entity_name|signal_name}: {signal|entity} is "{yes|no}";

Equivalent Register Removal Verilog Syntax Example

Place Equivalent Register Removal immediately before the module or signal declaration:

(* equivalent_register_removal = "{yes|no}" *)

Equivalent Register Removal XCF Syntax Example One

MODEL "entity_name" equivalent_register_removal={yes|no|true|false};

Equivalent Register Removal XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" equivalent_register_removal={yes|no|true|false};

END;

Equivalent Register Removal XST Command Line Syntax Example

Define Equivalent Register Removal globally with the – equivalent_register_removal command line option of the run command:

-equivalent_register_removal {yes|no}

The default is yes.

Equivalent Register Removal Project Navigator Syntax Example

Define Equivalent Register Removal globally in Project Navigator > Process Properties > Xilinx-Specific Options > Equivalent Register Removal.

FSM Encoding Algorithm (FSM_ENCODING)

FSM Encoding Algorithm (FSM_ENCODING) selects the finite state machine coding technique. In order to select a value for the FSM Encoding Algorithm, Automatic FSM Extraction must be enabled.

FSM Encoding Algorithm values are:

•Auto

•One-Hot

•Compact

•Sequential

•Gray

•Johnson

10.1

•Speed1

•User

FSM Encoding Algorithm defaults to auto. The best coding technique is automatically selected for each individual state machine.

FSM Encoding Algorithm Architecture Support

FSM Encoding Algorithm is architecture independent.

FSM Encoding Algorithm Applicable Elements

FSM Encoding Algorithm applies globally, or to a VHDL entity, Verilog module, or signal.

FSM Encoding Algorithm Propagation Rules

FSM Encoding Algorithm applies to the entity, module, or signal to which it is attached.

FSM Encoding Algorithm Syntax Examples

Following are syntax examples using FSM Encoding Algorithm with particular tools or methods. If a tool or method is not listed, FSM Encoding Algorithm may not be used with it.

FSM Encoding Algorithm VHDL Syntax Example

Before using FSM Encoding Algorithm, declare it with the following syntax:

attribute fsm_encoding: string;

After declaring FSM Encoding Algorithm, specify the VHDL constraint:

attribute fsm_encoding of {entity_name|signal_name}: {entity|signal} is "{auto|one-hot

|compact|sequential|gray|johnson|speed1|user}";

The default is auto.

FSM Encoding Algorithm Verilog Syntax Example

Place FSM Encoding Algorithm immediately before the module or signal declaration:

(* fsm_encoding = "{auto|one-hot |compact|sequential|gray|johnson|speed1|user}" *)

The default is auto.

FSM Encoding Algorithm XCF Syntax Example One

MODEL "entity_name" fsm_encoding={auto|one-hot |compact|sequential|gray|johnson|speed1|user};

FSM Encoding Algorithm XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" fsm_encoding={auto|one-hot |compact|sequential|gray|johnson|speed1|user};

END;

FSM Encoding Algorithm XST Command Line Syntax Example

Define FSM Encoding Algorithm globally with the –fsm_encoding command line option of the run command:

-fsm_encoding {auto|one-hot |compact|sequential|gray|johnson|speed1|user}

The default is auto.

FSM Encoding Algorithm Project Navigator Syntax Example

Set FSM Encoding (-fsm_encoding) and Automatic FSM Extraction (-fsm_extract) options in Project Navigator > Process Properties > HDL Options > FSM

Encoding Algorithm.

These options are:

•If the FSM Encoding Algorithm menu is set to None, and -fsm_extract is set to no, -fsm_encoding has no influence on the synthesis.

•In all other cases, -fsm_extract is set to yes and -fsm_encoding is set to the value selected in the menu. For more information, see “Automatic FSM Extraction (FSM_EXTRACT)”

Mux Extraction (MUX_EXTRACT)

Mux Extraction (MUX_EXTRACT) enables or disables multiplexer macro inference.

Mux Extraction values are:

•yes

•no

•force

•true (XCF only)

•false (XCF only)

By default, multiplexer inference is enabled (yes). For each identified multiplexer description, based on some internal decision rules, XST actually creates a macro or optimizes it with the rest of the logic. The force value overrides those decision rules, and forces XST to create the MUX macro.

Mux Extraction Architecture Support

Mux Extraction is architecture independent.

Mux Extraction Applicable Elements

Mux Extraction applies globally, or to a VHDL entity, a Verilog module, or signal.

Mux Extraction Propagation Rules

Mux Extraction applies to the entity, module, or signal to which it is attached.

Mux Extraction Syntax Examples

Following are syntax examples using Mux Extraction with particular tools or methods. If a tool or method is not listed, Mux Extraction may not be used with it.

10.1

Mux Extraction VHDL Syntax Example

Before using Mux Extraction, declare it with the following syntax:

attribute mux_extract: string;

After declaring Mux Extraction, specify the VHDL constraint:

attribute mux_extract of {signal_name|entity_name}: {entity|signal} is "{yes|no|force}";

The default is yes.

Mux Extraction Verilog Syntax Example

Place Mux Extraction immediately before the module or signal declaration:

(* mux_extract = "{yes|no|force}" *)

The default is yes.

Mux Extraction XCF Syntax Example One

MODEL "entity_name" mux_extract={yes|no|true|false|force};

Mux Extraction XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" mux_extract={yes|no|true|false|force};

END;

Mux Extraction XST Command Line Syntax Example

Define Mux Extraction globally with the –mux_extract command line option of the run command:

-mux_extract {yes|no|force}

The default is yes.

Mux Extraction Project Navigator Syntax Example

Define Mux Extraction globally in Project Navigator > Process Properties > HDL Options.

Register Power Up (REGISTER_POWERUP)

XST does not automatically calculate and enforce register power-up values. You must explicitly specify them if needed using Register Power Up (REGISTER_POWERUP). This XST synthesis constraint can be assigned to a VHDL enumerated type, or it may be directly attached to a VHDL signal or a Verilog register node through a VHDL attribute or Verilog meta comment. The value may be a binary string or a symbolic code value.

Register Power Up Architecture Support

Register Power Up applies to the following devices only:

•All CPLD devices

•Spartan-3A

Register Power Up Applicable Elements

Register Power Up applies to signals and types.

Register Power Up Propagation Rules

Register Power Up applies to the signal or type to which it is attached.

Register Power Up Syntax Examples

Following are syntax examples using Register Power Up with particular tools or methods. If a tool or method is not listed, Register Power Up may not be used with it.

Register Power Up VHDL Syntax Example One

The register is defined with a predefined VHDL type such as std_logic_vector. The Register Power Up value is necessarily a binary code.

signal myreg : std_logic_vector (3 downto 0);

attribute register_powerup of myreg : signal is "0001";

Register Power Up VHDL Syntax Example Two

The register is defined with an enumerated type (symbolic state machine). Register Power Up is attached to the signal and its value is one of the symbolic states defined. Actual power-up code differs depending on how the state machine is encoded.

type state_type is (s1, s2, s3, s4, s5);

signal state1 : state_type;

Register Power Up VHDL Syntax Example Three

Register Power Up is attached to an enumerated type. All registers defined with that type inherit the constraint.

type state_type is (s1, s2, s3, s4, s5);

attribute register_powerup of state_type : type is "s1"; signal state1, state2 : state_type;

Register Power Up VHDL Syntax Example Four

For enumerated type objects, the power-up value may also be defined as a binary code. However, if automatic encoding is enabled and leads to a different encoding scheme (in particular a different code width), the power-up value is ignored.

type state_type is (s1, s2, s3, s4, s5);

attribute enum_encoding of state_type : type is "001 011 010 100 111"; attribute register_powerup of state_type : type is "100";

signal state1 : state_type;

Register Power Up Verilog Syntax Example

Place Register Power Up immediately before the signal declaration:

(* register_powerup = "<value>" *)

Register Power Up XCF Syntax Example

BEGIN MODEL "entity_name"

NET "signal_name" register_powerup="string";

END;

10.1