Finite State Machines (FSMs) HDL Coding Techniques

(*ram_style="pipe_distributed"*)

else

pipe_reg <= RAM[addr]; do <= pipe_reg;

end

endmodule

Finite State Machines (FSMs) HDL Coding Techniques

This section discusses Finite State Machines (FSMs) HDL Coding Techniques, and includes:

•“About Finite State Machines (FSMs)”

•“Describing Finite State Machines (FSMs)”

•“State Encoding Techniques”

•“RAM-Based FSM Synthesis”

•“Safe FSM Implementation”

•“Finite State Machines Log File”

•“Finite State Machines Related Constraints”

•“Finite State Machines Coding Examples”

About Finite State Machines (FSMs)

XST proposes a large set of templates to describe Finite State Machines (FSMs). By default, XST tries to distinguish FSMs from VHDL or Verilog code, and apply several state encoding techniques (it can re-encode your initial encoding) to obtain better performance or less area. To disable FSM extraction, use the “Automatic FSM Extraction (FSM_EXTRACT)” constraint. XST can handle only synchronous state machines.

10.1

Describing Finite State Machines (FSMs)

There are many ways to describe FSMs. A traditional FSM representation incorporates Mealy and Moore machines, as shown in Figure 2-74, “FSM Representation Incorporating Mealy and Moore Machines Diagram.” XST supports both models.

Figure 2-74: FSM Representation Incorporating Mealy and Moore Machines Diagram

For HDL, process (VHDL) and always blocks (Verilog) are the most suitable ways for describing FSMs. Xilinx uses process to refer to both VHDL processes and Verilog always blocks.

You may have several processes (1, 2 or 3) in your description, depending upon how you consider and decompose the different parts of the preceding model. Following is an example of the Moore Machine with Asynchronous Reset, RESET.

•4 states: s1, s2, s3, s4

•5 transitions

•1 input: x1

•1 output: outp

This model is represented by the following bubble diagram:

S4

Figure 2-75: Bubble Diagram

10.1

State Registers

State registers must be initialized with an asynchronous or synchronous signal, or have the power-up value defined by “Register Power Up (REGISTER_POWERUP)” Otherwise, XST does not recognize FSM. See “Registers HDL Coding Techniques” for coding examples on how to write Asynchronous and Synchronous initialization signals.

In VHDL, the type of a state register can be a different type, such as:

•integer

•bit_vector

•std_logic_vector

But it is common and convenient to define an enumerated type containing all possible state values and to declare your state register with that type.

In Verilog, the type of state register can be an integer or a set of defined parameters. In the following Verilog examples the state assignments could have been made as follows:

parameter [3:0] s1 = 4'b0001, s2 = 4'b0010, s3 = 4'b0100, s4 = 4'b1000;

reg [3:0] state;

These parameters can be modified to represent different state encoding schemes.

Next State Equations

Next state equations can be described directly in the sequential process or in a distinct combinational process. The simplest coding example is based on a Case statement. If using a separate combinational process, its sensitivity list should contain the state signal and all FSM inputs.

Unreachable States

XST can detect unreachable states in an FSM. It lists them in the log file in the HDL

Synthesis step.

FSM Outputs

Non-registered outputs are described either in the combinational process or in concurrent assignments. Registered outputs must be assigned within the sequential process.

FSM Inputs

Registered inputs are described using internal signals, which are assigned in the sequential process.

State Encoding Techniques

XST supports the following state encoding techniques:

•“Auto State Encoding”

•“One-Hot State Encoding”

•“Gray State Encoding”

10.1

•“Compact State Encoding”

•“Johnson State Encoding”

•“Sequential State Encoding”

•“Speed1 State Encoding”

•“User State Encoding”

Auto State Encoding

In Auto State Encoding, XST tries to select the best suited encoding algorithm for each FSM.

One-Hot State Encoding

One-Hot State Encoding is the default encoding scheme. Its principle is to associate one code bit and also one flip-flop to each state. At a given clock cycle during operation, one and only one bit of the state variable is asserted. Only two bits toggle during a transition between two states. One-Hot State Encoding is appropriate with most FPGA targets where a large number of flip-flops are available. It is also a good alternative when trying to optimize speed or to reduce power dissipation.

Gray State Encoding

Gray State Encoding guarantees that only one bit switches between two consecutive states. It is appropriate for controllers exhibiting long paths without branching. In addition, this coding technique minimizes hazards and glitches. Very good results can be obtained when implementing the state register with T flip-flops.

Compact State Encoding

Compact State Encoding consists of minimizing the number of bits in the state variables and flip-flops. This technique is based on hypercube immersion. Compact State Encoding is appropriate when trying to optimize area.

Johnson State Encoding

Like Gray State Encoding, Johnson State Encoding shows benefits with state machines containing long paths with no branching.

Sequential State Encoding

Sequential State Encoding consists of identifying long paths and applying successive radix two codes to the states on these paths. Next state equations are minimized.

Speed1 State Encoding

Speed1 State Encoding is oriented for speed optimization. The number of bits for a state register depends on the particular FSM, but generally it is greater than the number of FSM states.

User State Encoding

In User State Encoding, XST uses the original encoding specified in the HDL file. For example, if you use enumerated types for a state register, use the “Enumerated Encoding