Estimation of Maximum Combinational Path Delay is 8.281ns with an area of five slices.

By default, XST reads Electronic Data Interchange Format (EDIF) and NGC cores from the current (project) directory. If the cores are not in the project directory, specify the directory in which the cores are located with “Cores Search Directories (–sd)”

Specifying INIT and RLOC

This section discusses Specifying INIT and “RLOC” and includes:

•“About Specifying INIT and RLOC”

•“Passing an INIT Value Via the LUT_MAP Constraint Coding Examples”

•“Specifying INIT Value for a Flip-Flop Coding Examples”

•“Specifying INIT and RLOC Values for a Flip-Flop Coding Examples”

About Specifying INIT and RLOC

Use the UNISIM library to directly instantiate LUT components in your HDL code. To specify a function that a particular LUT must execute, apply an INIT constraint to the instance of the LUT. To place an instantiated LUT or register in a particular slice of the chip, attach an “RLOC” constraint to the same instance.

It is not always convenient to calculate INIT functions and different methods that can be used to achieve this. Instead, you can describe the function that you want to map onto a single LUT in your VHDL or Verilog code in a separate block. Attaching a LUT_MAP constraint to this block indicates to XST that this block must be mapped on a single LUT. XST automatically calculates the INIT value for the LUT and preserves this LUT during optimization. XST automatically recognizes the XC_MAP constraint supported by Synplicity.

Passing an INIT Value Via the LUT_MAP Constraint Coding Examples

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip

The following coding examples show how to pass an INIT value using the LUT_MAP constraint:

•“Passing an INIT Value Via the LUT_MAP Constraint VHDL Coding Example”

•“Passing an INIT Value Via the LUT_MAP Constraint Verilog Coding Example”

In these examples, the top block contains the instantiation of two AND gates, described in and_one and and_two blocks. XST generates two LUT2s and does not merge them. For more information, see “Map Entity on a Single LUT (LUT_MAP)”

Passing an INIT Value Via the LUT_MAP Constraint VHDL Coding Example

--

-- Mapping on LUTs via LUT_MAP constraint

--

library ieee;

use ieee.std_logic_1164.all; entity and_one is

port (A, B : in std_logic; REZ : out std_logic);

attribute LUT_MAP: string;

attribute LUT_MAP of and_one: entity is "yes"; end and_one;

architecture beh of and_one is begin

REZ <= A and B; end beh;

--------------------------------------------------

library ieee;

use ieee.std_logic_1164.all; entity and_two is

port(A, B : in std_logic; REZ : out std_logic);

attribute LUT_MAP: string;

attribute LUT_MAP of and_two: entity is "yes"; end and_two;

architecture beh of and_two is begin

REZ <= A or B; end beh;

--------------------------------------------------

library ieee;

use ieee.std_logic_1164.all; entity inits_rlocs_1 is

port(A,B,C : in std_logic; REZ : out std_logic);

end inits_rlocs_1;

architecture beh of inits_rlocs_1 is

component and_one port(A, B : in std_logic;

REZ : out std_logic); end component;

component and_two port(A, B : in std_logic;

REZ : out std_logic); end component;

signal tmp: std_logic; begin

inst_and_one: and_one port map (A => A, B => B, REZ => tmp); inst_and_two: and_two port map (A => tmp, B => C, REZ => REZ);

end beh;

Passing an INIT Value Via the LUT_MAP Constraint Verilog Coding Example

//

// Mapping on LUTs via LUT_MAP constraint

//

10.1

or or_inst(REZ, A, B);

endmodule

// --------------------------------------------------

module v_inits_rlocs_1 (A, B, C, REZ); input A, B, C;

output REZ;

wire tmp;

v_and_one inst_and_one (A, B, tmp); v_and_two inst_and_two (tmp, C, REZ);

endmodule

Specifying INIT Value for a Flip-Flop Coding Examples

This section gives the following Specifying INIT Value for a Flip-Flop coding examples:

•“”

•“Specifying INIT Value for a Flip-Flop Verilog Coding Example”

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip

If a function cannot be mapped on a single LUT, XST issues an error message and interrupts synthesis. To define an INIT value for a flip-flop or a shift register, described at RTL level, assign its initial value in the signal declaration stage. This value is not ignored during synthesis and is propagated to the final netlist as an INIT constraint attached to the flip-flop or shift register.

In the following coding examples, a 4-bit register is inferred for signal tmp.

An INIT value equal 1011 is attached to the inferred register and propagated to the final netlist.

Specifying INIT Value for a Flip-Flop VHDL Coding Example

--

-- Specification on an INIT value for a flip-flop, described at RTL level

--

library ieee;

use ieee.std_logic_1164.all;

entity inits_rlocs_2 is

port (CLK : in std_logic;

DI : in std_logic_vector(3 downto 0); DO : out std_logic_vector(3 downto 0));

end inits_rlocs_2;

architecture beh of inits_rlocs_2 is signal tmp: std_logic_vector(3 downto 0):="1011";

begin

process (CLK) begin

if (clk'event and clk='1') then tmp <= DI;

end if; end process;

DO <= tmp;

end beh;

Specifying INIT Value for a Flip-Flop Verilog Coding Example

//

//Specification on an INIT value for a flip-flop,

//described at RTL level

//

module v_inits_rlocs_2 (clk, di, do);

initial begin

tmp = 4'b1011;

end

always @(posedge clk) begin

tmp <= di;

end

assign do = tmp;

endmodule

10.1