•VHDL allows the design of a system to be simulated before being implemented and manufactured. This feature allows you to test for correctness without the delay and expense of hardware prototyping.

•VHDL provides a mechanism for easily producing a detailed, device-dependent version of a design to be synthesized from a more abstract specification. This feature allows you to concentrate on more strategic design decisions, and reduce the overall time to market for the design.

VHDL IEEE Support

This section discusses VHDL IEEE Support, and includes:

•“About VHDL IEEE Support”

•“VHDL IEEE Conflicts”

•“Non-LRM Compliant Constructs in VHDL”

About VHDL IEEE Support

XST supports:

•VHDL IEEE std 1076-1987

•VHDL IEEE std 1076-1993

•VHDL IEEE std 1076-2006 (partially implemented)

XST allows instantiation for VHDL IEEE std 1076-2006 when:

•The formal port is a buffer and the associated actual is an out

•The formal port is an out and the associated actual is a buffer

VHDL IEEE Conflicts

VHDL IEEE std 1076-1987 constructs are accepted if they do not conflict with VHDL IEEE std 1076-1993. In case of a conflict, Std 1076-1993 behavior overrides std 1076-1987.

In cases where:

•Std 1076-1993 requires a construct to be an erroneous case, but

•Std 1076-1987 accepts it,

XST issues a warning instead of an error. An error would stop analysis.

VHDL IEEE Conflict Example

Following is an example of a VHDL IEEE conflict:

•Std 1076-1993 requires an impure function to use the impure keyword while declaring a function.

•Std 1076-1987 has no such requirement.

In this case, XST:

•Accepts the VHDL code written for Std 1076-1987

•Issues a warning stating Std 1076-1993 behavior