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Chapter 7

XST Verilog Language Support

This chapter (XST Verilog Language Support) describes XST support for Verilog constructs and meta comments. This chapter includes:

•“About XST Verilog Language Support”

•“Behavioral Verilog”

•“Variable Part Selects”

•“Structural Verilog Features”

•“Verilog Parameters”

•“Verilog Parameter and Attribute Conflicts”

•“Verilog Limitations in XST”

•“Verilog Attributes and Meta Comments”

•“Verilog Constructs Supported in XST”

•“Verilog System Tasks and Functions Supported in XST”

•“Verilog Primitives”

•“Verilog Reserved Keywords”

•“Verilog-2001 Support in XST”

For more information on Verilog design constraints and options, see “XST Design Constraints.” For more information on Verilog attribute syntax, see “Verilog-2001 Attributes.” For more information on setting Verilog options in the Process window of Project Navigator, see “XST General Constraints.”

About XST Verilog Language Support

Complex circuits are commonly designed using a top down methodology. Various specification levels are required at each stage of the design process. As an example, at the architectural level, a specification may correspond to a block diagram or an Algorithmic State Machine (ASM) chart. A block or ASM stage corresponds to a register transfer block (for example register, adder, counter, multiplexer, glue logic, finite state machine) where the connections are N-bit wires. A Hardware Description Language (HDL) such as Verilog allows the expression of notations such as ASM charts and circuit diagrams in a computer language.

Verilog provides both behavioral and structural language structures. These structures allow expressing design objects at high and low levels of abstraction. Designing hardware with a language such as Verilog allows using software concepts such as parallel processing and object-oriented programming. Verilog has a syntax similar to C and Pascal, and is supported by XST as IEEE 1364.

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