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Multiply Adder/Subtractors HDL Coding Techniques
Multiply Adder/Subtractors HDL Coding Techniques
This section discusses Multiply Adder/Subtractors HDL Coding Techniques, and includes:
•“About Multiply Adder/Subtractors”
•“Multiply Adder/Subtractors in Virtex-4 and Virtex- 5 Devices”
•“Multiply Adder/Subtractors Log File”
•“Multiply Adder/Subtractors Related Constraints”
•“Multiply Adder/Subtractors Coding Examples”
About Multiply Adder/Subtractors
The Multiply Adder/Subtractor macro is a complex macro consisting of several basic macros such as multipliers, adder/subtractors and registers. The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources in Virtex-4 and Virtex-5 devices.
Multiply Adder/Subtractors in Virtex-4 and Virtex- 5 Devices
XST supports the registered version of this macro and can push up to 2 levels of input registers on multiplier inputs, 1 register level on the Adder/Subtractor input and 1 level of output register into the DSP48 block. If the Carry In or Add/Sub operation selectors are registered, XST pushes these registers into the DSP48. In addition, the multiplication operation could be registered as well.
XST can implement a multiply adder/subtractor in a DSP48 block if its implementation requires only a single DSP48 resource. If the macro exceeds the limits of a single DSP48, XST processes it as two separate Multiplier and Adder/Subtractor macros, making independent decisions on each macro. For more information, see “Multipliers HDL Coding Techniques” and “Adders, Subtractors, and Adders/Subtractors HDL Coding Techniques”
Macro implementation on DSP48 blocks is controlled by the “Use DSP48 (USE_DSP48)” constraint or command line option, with default value of auto. In this mode, XST implements multiply adder/subtractors taking into account DSP48 resources in the device.
In auto mode, use the “DSP Utilization Ratio (DSP_UTILIZATION_RATIO)” constraint to control DSP48 resources for the synthesis. By default, XST tries to utilize all available DSP48 resources. For more information, see “DSP48 Block Resources.”
To deliver the best performance, XST by default tries to infer and implement the maximum macro configuration, including as many registers in the DSP48 as possible. To shape a macro in a specific way, use the “Keep (KEEP)” constraint. For example, to exclude the first register stage from the DSP48, place “Keep (KEEP)” constraints on the outputs of these registers.
In the log file, XST reports the details of inferred multipliers, adders, subtractors, and registers at the HDL Synthesis step. XST reports about inferred MACs during the Advanced HDL Synthesis Step where the MAC implementation mechanism takes place.
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Multiply Adder/Subtractors Log File
In the log file, XST reports the details of inferred multipliers, adder/subtractors and registers at the HDL Synthesis step. The composition of multiply adder/subtractor macros happens at the Advanced HDL Synthesis step. XST reports information about inferred MACs, because they are implemented within the MAC implementation mechanism.
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* HDL Synthesis *
====================================================================
Synthesizing Unit <multipliers_6>.
Related source file is "multipliers_6.vhd". Found 8-bit register for signal <A_reg1>. Found 8-bit register for signal <A_reg2>. Found 8-bit register for signal <B_reg1>. Found 8-bit register for signal <B_reg2>. Found 8x8-bit multiplier for signal <mult>. Found 16-bit addsub for signal <multaddsub>. Summary:
inferred 32 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Multiplier(s).
Unit <multipliers_6> synthesized.
...
====================================================================
* Advanced HDL Synthesis *
====================================================================
...
Synthesizing (advanced) Unit <Mmult_mult>.
Multiplier <Mmult_mult> in block <multipliers_6> and adder/subtractor <Maddsub_multaddsub> in block <multipliers_6> are combined into a MAC<Mmac_Maddsub_multaddsub>.
The following registers are also absorbed by the MAC: <A_reg2> in block <multipliers_6>, <A_reg1> in block <multipliers_6>, <B_reg2> in block <multipliers_6>, <B_reg1> in block <multipliers_6>.
Unit <Mmult_mult> synthesized (advanced).
====================================================================
HDL Synthesis Report
Macro Statistics |
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# MACs |
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8x8-to-16-bit MAC |
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1 |
====================================================================
Multiply Adder/Subtractors Related Constraints
•“Use DSP48 (USE_DSP48)”
•“DSP Utilization Ratio (DSP_UTILIZATION_RATIO)”
•“Keep (KEEP)”
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Multiply Adder/Subtractors HDL Coding Techniques
Multiply Adder/Subtractors Coding Examples
The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.
•“Multiplier Adder With 2 Register Levels on Multiplier Inputs”
•“Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs”
Multiplier Adder With 2 Register Levels on Multiplier Inputs
This section discusses Multiplier Adder With 2 Register Levels on Multiplier Inputs, and includes:
•“Multiplier Adder With 2 Register Levels on Multiplier Inputs Diagram”
•“Multiplier Adder With 2 Register Levels on Multiplier Inputs Pin Descriptions”
•“Multiplier Adder With 2 Register Levels on Multiplier Inputs VHDL Coding Example”
•“Multiplier Adder With 2 Register Levels on Multiplier Inputs Verilog Coding Example”
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ADD_SUB |
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Figure 2-47: Multiplier Adder With 2 Register Levels on Multiplier Inputs Diagram |
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Table 2-59: |
Multiplier Adder With 2 Register Levels on Multiplier Inputs Pin Descriptions |
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IO Pins |
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Description |
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clk |
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Positive-Edge Clock |
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A, B, C |
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MULT-Add Operands |
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RES |
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MULT-Add Result |
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Multiplier Adder With 2 Register Levels on Multiplier Inputs VHDL Coding Example
--
-- Multiplier Adder with 2 Register Levels on Multiplier Inputs
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multipliers_5 is
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generic (p_width: integer:=8); port (clk : in std_logic;
A, B, C : in std_logic_vector(p_width-1 downto 0); RES : out std_logic_vector(p_width*2-1 downto 0));
end multipliers_5;
architecture beh of multipliers_5 is signal A_reg1, A_reg2,
B_reg1, B_reg2 : std_logic_vector(p_width-1 downto 0); signal multaddsub : std_logic_vector(p_width*2-1 downto 0);
begin
multaddsub <= A_reg2 * B_reg2 + C;
process (clk) begin
if (clk'event and clk='1') then A_reg1 <= A; A_reg2 <= A_reg1; B_reg1 <= B; B_reg2 <= B_reg1;
end if; end process;
RES <= multaddsub;
end beh;
Multiplier Adder With 2 Register Levels on Multiplier Inputs Verilog Coding Example
//
// Multiplier Adder with 2 Register Levels on Multiplier Inputs
//
module v_multipliers_5 (clk, A, B, C, RES);
input |
clk; |
input |
[7:0] A; |
input |
[7:0] B; |
input |
[7:0] C; |
output |
[15:0] RES; |
reg |
[7:0] A_reg1, A_reg2, B_reg1, B_reg2; |
wire |
[15:0] multaddsub; |
always @(posedge clk) begin
A_reg1 <= A; A_reg2 <= A_reg1; B_reg1 <= B; B_reg2 <= B_reg1;
end
assign multaddsub = A_reg2 * B_reg2 + C; assign RES = multaddsub;
endmodule
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Multiply Adder/Subtractors HDL Coding Techniques
Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs
This section discusses Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs, and includes:
•“Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs Diagram”
•“Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs Pin Descriptions”
•“Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs VHDL Coding Example”
•“Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs Verilog Coding Example”
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Figure 2-48: Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs
Diagram
Table 2-60: Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs Pin Descriptions
IO Pins |
Description |
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clk |
Positive-Edge Clock |
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add_sub |
AddSub Selector |
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RES |
MULT-AddSub Result |
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Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs VHDL Coding
Example
--
--Multiplier Adder/Subtractor with
--2 Register Levels on Multiplier Inputs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multipliers_6 is
generic (p_width: integer:=8);
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port (clk,add_sub: in std_logic;
A, B, C: in std_logic_vector(p_width-1 downto 0); RES: out std_logic_vector(p_width*2-1 downto 0));
end multipliers_6;
architecture beh of multipliers_6 is signal A_reg1, A_reg2,
B_reg1, B_reg2 : std_logic_vector(p_width-1 downto 0); signal mult, multaddsub : std_logic_vector(p_width*2-1 downto 0);
begin
mult <= A_reg2 * B_reg2;
multaddsub <= C + mult when add_sub = '1' else C - mult;
process (clk) begin
if (clk'event and clk='1') then A_reg1 <= A; A_reg2 <= A_reg1; B_reg1 <= B; B_reg2 <= B_reg1;
end if; end process;
RES <= multaddsub;
end beh;
Multiplier Adder/Subtractor With 2 Register Levels On Multiplier Inputs Verilog Coding
Example
//
//Multiplier Adder/Subtractor with
//2 Register Levels on Multiplier Inputs
module v_multipliers_6 (clk, add_sub, A, B, C, RES);
input |
clk,add_sub; |
input |
[7:0] A; |
input |
[7:0] B; |
input |
[7:0] C; |
output |
[15:0] RES; |
reg |
[7:0] A_reg1, A_reg2, B_reg1, B_reg2; |
wire |
[15:0] mult, multaddsub; |
always |
@(posedge clk) |
begin |
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A_reg1 <= A; A_reg2 <= A_reg1; |
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B_reg1 <= B; B_reg2 <= B_reg1; |
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end |
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assign |
mult = A_reg2 * B_reg2; |
assign |
multaddsub = add_sub ? C + mult : C - mult; |
assign |
RES = multaddsub; |
endmodule
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