Verilog Parameters

input C; input CLR; input D; endmodule

(* BOX_TYPE="PRIMITIVE" *) // Verilog-2001 module BUFG ( O, I);

output O; input I; endmodule

Verilog Parameters

Verilog modules allow you to define constants known as parameters. Parameters can be passed to module instances to define circuits of arbitrary widths. Parameters form the basis of creating and using parameterized blocks in a design to achieve hierarchy and stimulate modular design techniques.

Verilog Parameters Coding Example

The following Verilog coding example shows the use of parameters. Null string parameters are not supported:

module lpm_reg (out, in, en, reset, clk); parameter SIZE = 1;

input in, en, reset, clk; output out;

lpm_reg #8 buf_373 (sys_out, sys_in, sys_en, sys_reset, sysclk);

...

endmodule

Instantiation of the module lpm_reg with a instantiation width of 8 causes the instance buf_373 to be 8 bits wide.

The “Generics (-generics)” command line option allows you to redefine parameters (Verilog) values defined in the top-level design block. This allows you to easily modify the design configuration without any Hardware Description Language (HDL) source modifications, such as for IP core generation and testing flows.

10.1