Black Boxes HDL Coding Techniques

Black Boxes HDL Coding Techniques

This section discusses Black Boxes HDL Coding Techniques, and includes:

•“About Black Boxes”

•“Black Box Log File”

•“Black Box Related Constraints”

•“Black Box Coding Examples”

About Black Boxes

Your design may contain Electronic Data Interchange Format (EDIF) or NGC files generated by synthesis tools, schematic editors or any other design entry mechanism. These modules must be instantiated in your code to be connected to the rest of your design. To do so in XST, use Black Box instantiation in the VHDL or Verilog code. The netlist is propagated to the final top-level netlist without being processed by XST. Moreover, XST enables you to attach specific constraints to these Black Box instantiations, which are passed to the NGC file.

In addition, you may have a design block for which you have an RTL model, as well as your own implementation of this block in the form of an EDIF netlist. The RTL model is valid for simulation purposes only. Use the “BoxType (BOX_TYPE)” constraint to direct XST to skip synthesis of this RTL code and create a Black Box. The EDIF netlist is linked to the synthesized design during NGDBuild. For more information, see “XST General Constraints” and the Xilinx Constraints Guide.

Once you make a design a Black Box, each instance of that design is a Black Box. While you can attach constraints to the instance, XST ignores any constraint attached to the original design.

Black Box Log File

From the flow point of view, the recognition of Black Boxes in XST is done before macro inference. Therefore the log file differs from the one generated for other macros.

...

Analyzing Entity <black_b> (Architecture <archi>).

WARNING:Xst:766 - black_box_1.vhd (Line 15). Generating a Black Box for component <my_block>.

Entity <black_b> analyzed. Unit <black_b> generated

....

Black Box Related Constraints

•“BoxType (BOX_TYPE)”

“BoxType (BOX_TYPE)” was introduced for Virtex Primitive instantiation in XST. See “Virtex Primitive Support” before using “BoxType (BOX_TYPE).”

10.1

Black Box Coding Examples

This section discusses Black Boxes, and includes:

•“Black Box VHDL Coding Example”

•“Black Box Verilog Coding Example”

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

Black Box VHDL Coding Example

--

-- Black Box

--

library ieee;

use ieee.std_logic_1164.all;

entity black_box_1 is

port(DI_1, DI_2 : in std_logic; DOUT : out std_logic);

end black_box_1;

architecture archi of black_box_1 is

component my_block

port (I1 : in std_logic; I2 : in std_logic; O : out std_logic);

end component;

begin

inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);

end archi;

Black Box Verilog Coding Example

//

// Black Box

//

module v_my_block (in1, in2, dout); input in1, in2;

output dout; endmodule

module v_black_box_1 (DI_1, DI_2, DOUT); input DI_1, DI_2;

output DOUT;

v_my_block inst (

.in1(DI_1),

.in2(DI_2),

.dout(DOUT));

endmodule

For more information on component instantiation, see your VHDL and Verilog language reference manuals.

10.1