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Multiply Accumulate HDL Coding Techniques
Multiply Accumulate HDL Coding Techniques
This section discusses Multiply Accumulate HDL Coding Techniques, and includes:
•“About Multiply Accumulate”
•“Multiply Accumulate in Virtex-4 and Virtex-5 Devices”
•“Multiply Accumulate Log File”
•“Multiply Accumulate Related Constraints”
•“Multiply Accumulate Coding Examples”
About Multiply Accumulate
The Multiply Accumulate macro is a complex macro consisting of several basic macros such as multipliers, accumulators, and registers. The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources in Virtex-4 and Virtex-5 devices.
Multiply Accumulate in Virtex-4 and Virtex-5 Devices
The Multiply Accumulate macro is a complex macro consisting of several basic macros as multipliers, accumulators, and registers. The recognition of this complex macro enables XST to implement it on dedicated DSP48 resources in Virtex-4 and Virtex-5 devices.
XST supports the registered version of this macro, and can push up to 2 levels of input registers into the DSP48 block. If Adder/Subtractor operation selectors are registered, XST pushes these registers into the DSP48. In addition, the multiplication operation could be registered as well.
XST can implement a multiply accumulate in a DSP48 block if its implementation requires only a single DSP48 resource. If the macro exceeds the limits of a single DSP48, XST processes it as two separate Multiplier and Accumulate macros, making independent decisions on each macro. For more information, see “Multipliers HDL Coding Techniques” and “Accumulators HDL Coding Techniques”
Macro implementation on DSP48 blocks is controlled by the “Use DSP48 (USE_DSP48)” constraint or command line option, with default value of auto. In auto mode, XST implements multiply accumulate taking into account available DSP48 resources in the device.
In auto mode, use “DSP Utilization Ratio (DSP_UTILIZATION_RATIO)” to control DSP48 resources. XST tries to utilize as many DSP48 resources as possible. For more information, see “DSP48 Block Resources.”
To deliver the best performance, XST by default tries to infer and implement the maximum macro configuration, including as many registers in the DSP48 as possible. To shape a macro in a specific way, use the “Keep (KEEP)” constraint. For example, to exclude the first register stage from the DSP48, place “Keep (KEEP)” constraints on the outputs of these registers.
In the log file, XST reports the details of inferred multipliers, accumulators and registers at the HDL Synthesis step. The composition of multiply accumulate macros happens at Advanced HDL Synthesis step.
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Multiply Accumulate Log File
In the log file, XST reports the details of inferred multipliers, accumulators and registers at the HDL Synthesis step. The composition of multiply accumulate macros happens at the Advanced HDL Synthesis step.
====================================================================
* HDL Synthesis *
====================================================================
...
Synthesizing Unit <multipliers_7a>.
Related source file is "multipliers_7a.vhd".
Found 8x8-bit multiplier for signal <$n0002> created at line 28.
Found 16-bit |
up accumulator for signal <accum>. |
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Found 16-bit |
register for signal <mult>. |
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Summary: |
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inferred |
1 |
Accumulator(s). |
inferred |
16 |
D-type flip-flop(s). |
inferred |
1 |
Multiplier(s). |
Unit <multipliers_7a> synthesized....
====================================================================
* Advanced HDL Synthesis *
====================================================================
...
Synthesizing (advanced) Unit <Mmult__n0002>.
Multiplier <Mmult__n0002> in block <multipliers_7a> and accumulator <accum> in block <multipliers_7a> are combined into a MAC<Mmac_accum>.
The following registers are also absorbed by the MAC: <mult> in block <multipliers_7a>.
Unit <Mmult__n0002> synthesized (advanced).
====================================================================
HDL Synthesis Report
Macro Statistics |
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# MACs |
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1 |
8x8-to-16-bit MAC |
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1 |
====================================================================
Multiply Accumulate Related Constraints
•“Use DSP48 (USE_DSP48)”
•“DSP Utilization Ratio (DSP_UTILIZATION_RATIO)”
•“Keep (KEEP)”
Multiply Accumulate Coding Examples
The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.
•“Multiplier Up Accumulate With Register After Multiplication”
•“Multiplier Up/Down Accumulate With Register After Multiplication”
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Multiply Accumulate HDL Coding Techniques
Multiplier Up Accumulate With Register After Multiplication
This section discusses Multiplier Up Accumulate With Register After Multiplication, and includes:
•“Multiplier Up Accumulate With Register After Multiplication”
•“Multiplier Up Accumulate With Register After Multiplication Pin Descriptions”
•“Multiplier Up Accumulate With Register After Multiplication VHDL Coding Example”
•“Multiplier Up Accumulate With Register After Multiplication Verilog Coding Example”
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RES |
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A |
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8 B 
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RESET |
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Figure 2-49: Multiplier Up Accumulate With Register After Multiplication
Table 2-61: |
Multiplier Up Accumulate With Register After Multiplication Pin Descriptions |
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IO Pins |
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Description |
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clk |
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Positive-Edge Clock |
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reset |
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Synchronous Reset |
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A, B |
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MAC Operands |
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RES |
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MAC Result |
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Multiplier Up Accumulate With Register After Multiplication VHDL Coding Example
--
-- Multiplier Up Accumulate with Register After Multiplication
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multipliers_7a is
generic (p_width: integer:=8); port (clk, reset: in std_logic;
A, B: in std_logic_vector(p_width-1 downto 0);
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RES: out std_logic_vector(p_width*2-1 downto 0)); end multipliers_7a;
architecture beh of multipliers_7a is
signal mult, accum: std_logic_vector(p_width*2-1 downto 0); begin
process (clk) begin
if (clk'event and clk='1') then if (reset = '1') then
accum <= (others => '0'); mult <= (others => '0');
else
accum <= accum + mult; mult <= A * B;
end if; end if;
end process;
RES <= accum;
end beh;
Multiplier Up Accumulate With Register After Multiplication Verilog Coding Example
//
// Multiplier Up Accumulate with Register After Multiplication
//
module v_multipliers_7a (clk, reset, A, B, RES);
input |
clk, reset; |
input |
[7:0] A; |
input |
[7:0] B; |
output |
[15:0] RES; |
reg |
[15:0] mult, accum; |
always |
@(posedge clk) |
begin |
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if |
(reset) |
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mult <= 16'b0000000000000000; |
else |
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mult <= A * B; |
end |
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always |
@(posedge clk) |
begin |
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if |
(reset) |
accum <= 16'b0000000000000000; else
accum <= accum + mult;
end
assign RES = accum;
endmodule
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Multiply Accumulate HDL Coding Techniques
Multiplier Up/Down Accumulate With Register After Multiplication
This section discusses Multiplier Up/Down Accumulate With Register After
Multiplication, and includes:
•“Multiplier Up/Down Accumulate With Register After Multiplication Diagram”
•“Multiplier Up/Down Accumulate With Register After Multiplication Pin Descriptions”
•“Multiplier Up/Down Accumulate With Register After Multiplication VHDL Coding Example”
•“Multiplier Up/Down Accumulate With Register After Multiplication Verilog Coding Example”
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B |
ADD_SUB |
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CLK |
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RESET |
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Figure 2-50: Multiplier Up/Down Accumulate With Register After Multiplication Diagram
Table 2-62: Multiplier Up/Down Accumulate With Register After Multiplication Pin
Descriptions
IO Pins |
Description |
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clk |
Positive-Edge Clock |
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reset |
Synchronous Reset |
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add_sub |
AddSub Selector |
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A, B |
MAC Operands |
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RES |
MAC Result |
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Multiplier Up/Down Accumulate With Register After Multiplication VHDL Coding Example
--
-- Multiplier Up/Down Accumulate with Register After Multiplication.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL; entity multipliers_7b is
generic (p_width: integer:=8);
port (clk, reset, add_sub: in std_logic;
A, B: in std_logic_vector(p_width-1 downto 0); RES: out std_logic_vector(p_width*2-1 downto 0));
end multipliers_7b;
architecture beh of multipliers_7b is
signal mult, accum: std_logic_vector(p_width*2-1 downto 0); begin
process (clk) begin
if (clk'event and clk='1') then if (reset = '1') then
accum <= (others => '0'); mult <= (others => '0');
else
if (add_sub = '1') then accum <= accum + mult;
else
accum <= accum - mult; end if;
mult <= A * B; end if;
end if; end process;
RES <= accum;
end beh;
Multiplier Up/Down Accumulate With Register After Multiplication Verilog Coding Example
//
// Multiplier Up/Down Accumulate with Register After Multiplication.
//
module v_multipliers_7b (clk, reset, add_sub, A, B, RES);
input |
clk, reset, add_sub; |
input |
[7:0] A; |
input |
[7:0] B; |
output |
[15:0] RES; |
reg |
[15:0] mult, accum; |
always |
@(posedge clk) |
begin |
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if |
(reset) |
mult <= 16'b0000000000000000; else
mult <= A * B;
end
always @(posedge clk) begin
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