Define Convert Tristates to Logic globally with the –tristate2logic command line option of the run command:

-tristate2logic {yes|no}

The default is yes.

Convert Tristates to Logic Project Navigator Syntax Example

Define Convert Tristates to Logic globally in Project Navigator > Process Properties > Xilinx-Specific Options > Convert Tristates to Logic.

Use Clock Enable (USE_CLOCK_ENABLE)

Clock Enable (USE_CLOCK_ENABLE) enables or disables the clock enable function in flip-flops. The disabling of the clock enable function is typically used for ASIC prototyping on FPGA devices.

By detecting Use Clock Enable with a value of no or false, XST avoids using CE resources in the final implementation. Moreover, for some designs, putting the Clock Enable function on the data input of the flip-flop allows better logic optimization and therefore better QOR. In auto mode, XST tries to estimate a trade off between using a dedicated clock enable input of a flip-flop input and putting clock enable logic on the D input of a flip-flop. In a case where a flip-flop is instantiated by you, XST removes the clock enable only if the Optimize Instantiated Primitives option is set to yes.

Use Clock Enable values are:

•auto (default)

•yes

•no

•true (XCF only)

•false (XCF only)

Use Clock Enable Architecture Support

Use Clock Enable applies to all FPGA devices. Use Clock Enable does not apply to CPLD devices.

Use Clock Enable Applicable Elements

Use Clock Enable applies to:

•An entire design through the XST command line

•A particular block (entity, architecture, component)

•A signal representing a flip-flop

•An instance representing an instantiated flip-flop

Use Clock Enable Propagation Rules

Use Clock Enable applies to an entity, component, module, signal, or instance to which it is attached.

Use Clock Enable Syntax Examples

Following are syntax examples using Use Clock Enable with particular tools or methods. If a tool or method is not listed, Use Clock Enable may not be used with it.

Use Clock Enable VHDL Syntax Example

Before using Use Clock Enable, declare it with the following syntax:

attribute use_clock_enable: string;

After declaring Use Clock Enable, specify the VHDL constraint:

attribute use_clock_enable of

{entity_name|component_name|signal_name|instance_name}: {entity|component|signal|label} is "{auto|yes|no}";

Use Clock Enable Verilog Syntax Example

Place Use Clock Enable immediately before the instance, module or signal declaration:

(* use_clock_enable = "{auto|yes|no}" *)

Use Clock Enable XCF Syntax Example One

MODEL "entity_name" use_clock_enable={auto|yes|no|true|false};

Use Clock Enable XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" use_clock_enable={auto|yes|no|true|false};

END;

Use Clock Enable XCF Syntax Example Three

BEGIN MODEL "entity_name"

INST "instance_name" use_clock_enable={auto|yes|no|true|false};

END;

Use Clock Enable XST Command Line Syntax Example

Define Use Clock Enable globally with the –use_clock_enable command line option of the run command:

-use_clock_enable {auto|yes|no}

The default is auto.

Use Clock Enable Project Navigator Syntax Example

Define Use Clock Enable globally in Project Navigator > Process Properties > Xilinx-Specific Options > Use Clock Enable.

Use Synchronous Set (USE_SYNC_SET)

Synchronous Set (USE_SYNC_SET) enables or disables the synchronous set function in flip-flops. The disabling of the synchronous set function is typically used for ASIC prototyping on FPGA devices. Detecting Use Synchronous Set with a value of no or false, XST avoids using synchronous reset resources in the final implementation. Moreover, for some designs, putting synchronous reset function on data input of the flipflop allows better logic optimization and therefore better QOR.

10.1

In auto mode, XST tries to estimate a trade off between using dedicated Synchronous Set input of a flip-flop input and putting Synchronous Set logic on the D input of a flip-flop. In a case where a flip-flop is instantiated by you, XST removes the synchronous reset only if the Optimize Instantiated Primitives option is set to yes.

Use Synchronous Set values are:

•auto (default)

•yes

•no

•true (XCF only)

•false (XCF only)

Use Synchronous Set Architecture Support

Use Synchronous Set applies to all FPGA devices. Use Synchronous Set does not apply to CPLD devices.

Use Synchronous Set Applicable Elements

Use Synchronous Set applies to:

•An entire design through the XST command line

•A particular block (entity, architecture, component)

•A signal representing a flip-flop

•An instance representing an instantiated flip-flop

Use Synchronous Set Propagation Rules

Use Synchronous Set applies to an entity, component, module, signal, or instance to which it is attached.

Use Synchronous Set Syntax Examples

Following are syntax examples using Use Synchronous Set with particular tools or methods. If a tool or method is not listed, Use Synchronous Set may not be used with it.

Use Synchronous Set VHDL Syntax Example

Before using Use Synchronous Set, declare it with the following syntax:

attribute use_sync_set: string;

After declaring Use Synchronous Set, specify the VHDL constraint:

attribute use_sync_set of

{entity_name|component_name|signal_name|instance_name}: {entity|component|signal|label} is "{auto|yes|no}";

Use Synchronous Set Verilog Syntax Example

Place Use Synchronous Set immediately before the instance, module or signal declaration:

(* use_sync_set = "{auto|yes|no}" *)

Use Synchronous Set XCF Syntax Example One

MODEL "entity_name" use_sync_set={auto|yes|no|true|false};

Use Synchronous Set XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" use_sync_set={auto|yes|no|true|false};

END;

Use Synchronous Set XCF Syntax Example Three

BEGIN MODEL "entity_name"

INST "instance_name" use_sync_set={auto|yes|no|true|false};

END;

Use Synchronous Set XST Command Line Syntax Example

Define Use Synchronous Set globally with the –use_sync_set command line option of the run command:

-use_sync_set {auto|yes|no}

The default is auto.

Use Synchronous Set Project Navigator Syntax Example

Define Use Synchronous Set globally in Project Navigator > Process

Properties > Xilinx-Specific Options > Use Synchronous Set.

Use Synchronous Reset (USE_SYNC_RESET)

Synchronous Reset (USE_SYNC_RESET) enables or disables the usage of synchronous reset function of flip-flops. The disabling of the Synchronous Reset function could be used for ASIC prototyping flow on FPGA devices.

Detecting Use Synchronous Reset with a value of no or false, XST avoids using synchronous reset resources in the final implementation. Moreover, for some designs, putting synchronous reset function on data input of the flip-flop allows better logic optimization and therefore better QOR.

In auto mode, XST tries to estimate a trade off between using a dedicated Synchronous Reset input on a flip-flop input and putting Synchronous Reset logic on the D input of a flip-flop. In a case where a flip-flop is instantiated by you, XST removes the synchronous reset only if the Optimize Instantiated Primitives option is set to yes.

Use Synchronous Reset values are:

•auto (default)

•yes

•no

•true (XCF only)

•false (XCF only)

Use Synchronous Reset Architecture Support

Use Synchronous Reset applies to all FPGA devices. Use Synchronous Reset does not apply to CPLD devices.

10.1

Use Synchronous Reset Applicable Elements

Use Synchronous Reset applies to:

•An entire design through the XST command line

•A particular block (entity, architecture, component)

•A signal representing a flip-flop

•An instance representing an instantiated flip-flop

Use Synchronous Reset Propagation Rules

Use Synchronous Reset applies to an entity, component, module, signal, or instance to which it is attached.

Use Synchronous Reset Syntax Examples

Following are syntax examples using Use Synchronous Reset with particular tools or methods. If a tool or method is not listed, Use Synchronous Reset may not be used with it.

Use Synchronous Reset VHDL Syntax Example

Before using Use Synchronous Reset, declare it with the following syntax:

attribute use_sync_reset: string;

After declaring Use Synchronous Reset, specify the VHDL constraint:

attribute use_sync_reset of

{entity_name|component_name|signal_name|instance_name}:

{entity|component|signal|label} is "{auto|yes|no}";

Use Synchronous Reset Verilog Syntax Example

Place this attribute immediately before the instance, module, or signal declaration:

(* use_sync_reset = "{auto|yes|no}" *)

Use Synchronous Reset XCF Syntax Example One

MODEL "entity_name" use_sync_reset={auto|yes|no|true|false};

Use Synchronous Reset XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" use_sync_reset={auto|yes|no|true|false};

END;

Use Synchronous Reset XCF Syntax Example Three

BEGIN MODEL "entity_name"

INST "instance_name" use_sync_reset={auto|yes|no|true|false};

END;

Use Synchronous Reset XST Command Line Syntax Example

Define Use Synchronous Reset globally with the –use_sync_reset command line option of the run command:

-use_sync_reset {auto|yes|no}

The default is auto.

Use Synchronous Reset Project Navigator Syntax Example

Define Use Synchronous Reset globally in Project Navigator > Process

Properties > Xilinx-Specific Options > Use Synchronous Reset.

Use DSP48 (USE_DSP48)

This option is called:

•Use DSP48 (Virtex-4 devices)

•Use DSP Block (Virtex-5 devices)

XST enables you to use the resources of the DSP48 blocks introduced in Virtex-4 devices. The default is auto. In auto mode, XST automatically implements such macros as MAC and accumulates on DSP48, but some of them as adders are implemented on slices. You have to force their implementation on DSP48 using a value of yes or true. For more information on supported macros and their implementation control, see “XST HDL Coding Techniques.”

Several macros (for example, MAC) that can be placed on DSP48 are in fact a composition of simpler macros such as multipliers, accumulators, and registers. To achieve the best performance, XST by default tries to infer and implement the maximum macro configuration. To shape a macro in a specific way, use the “Keep (KEEP)” constraint. For example, DSP48 allows you to implement a multiple with two input registers. To leave the first register stage outside of the DSP48, place the “Keep (KEEP)” constraint in their outputs.

Use DSP48 values are:

•auto (default)

•yes

•no

•true (XCF only)

•false (XCF only)

In auto mode you can control the number of available DSP48 resources for synthesis using “DSP Utilization Ratio (DSP_UTILIZATION_RATIO).” By default, XST tries to utilize, as much as possible, all available DSP48 resources. For more information, see “DSP48 Block Resources.”

Use DSP48 Architecture Support

Use DSP48 applies to the following FPGA devices only:

•Spartan-3A D

•Virtex-4, Virtex-5

Use DSP48 does not apply to CPLD devices.

Use DSP48 Applicable Elements

Use DSP48 applies to:

•An entire design through the XST command line

•A particular block (entity, architecture, component)

•A signal representing a macro described at the RTL level

10.1