end

B_OUT <= arb_onebit; endmodule

This sets the set/reset value on the register output at initial power up, but since this is dependent upon a local reset, the value changes whenever the local set/reset is activated.

Behavioral Verilog Arrays

Verilog allows arrays of reg and wires to be defined as shown in the following coding examples:

•“Behavioral Verilog Arrays Coding Example”

•“Structural Verilog Arrays Coding Example”

Behavioral Verilog Arrays Coding Example

The following coding example describes an array of 32 elements each, 4 bits wide which can be assigned in behavioral Verilog code:

reg [3:0] mem_array [31:0];

Structural Verilog Arrays Coding Example

The following coding example describes an array of 64 elements each 8 bits wide which can be assigned only in structural Verilog code:

wire [7:0] mem_array [63:0];

Behavioral Verilog Multi-Dimensional Arrays

This section discusses Behavioral Verilog Multi-Dimensional Arrays and includes:

•“About Behavioral Verilog Multi-Dimensional Arrays”

•“Behavioral Verilog Multi-Dimensional Arrays Coding Examples”

About Behavioral Verilog Multi-Dimensional Arrays

XST supports multi-dimensional array types of up to two dimensions. Multi-dimensional arrays can be any net or any variable data type. You can code assignments and arithmetic operations with arrays, but you cannot select more than one element of an array at one time. You cannot pass multi-dimensional arrays to system tasks or functions, or regular tasks or functions.