Behavioral Verilog Comments

Verilog supports two forms of comments as shown in Table 8-4, “Behavioral Verilog

Comments.” Verilog comments are similar to the comments used in a language such as

C++.

Table 8-4: Behavioral Verilog Comments

Behavioral Verilog Generate Statements

A generate statement allows you to dynamically create Verilog code from conditional statements. This allows you to create repetitive structures or structures that are appropriate only under certain conditions.

Structures likely to be created using a generate statement are:

•Primitive or module instances

•Initial or always procedural blocks

•Continuous assignments

•Net and variable declarations

•Parameter redefinitions

•Task or function definitions

XST supports the following generate statements:

•“Behavioral Verilog Generate For Statements”

•“Behavioral Verilog Generate If... else Statements”

•“Behavioral Verilog Generate Case Statements”

Behavioral Verilog Generate For Statements

Use a generate for loop to create one or more instances that can be placed inside a module. Use the generate for loop the same way you would a normal Verilog for loop, with the following limitations:

•The index for a generate for loop has a genvar variable.

•The assignments in the for loop control refers to the genvar variable.

•The contents of the for loop are enclosed by begin and end statements. The begin statement is named with a unique qualifier.

8-Bit Adder Using a Generate For Loop Behavioral Verilog Coding Example

generate genvar i;

for (i=0; i<=7; i=i+1) begin : for_name

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adder add (a[8*i+7 : 8*i], b[8*i+7 : 8*i], ci[i], sum_for[8*i+7 : 8*i], c0_or[i+1]);

end endgenerate

Behavioral Verilog Generate If... else Statements

Use a generate if... else statement inside a generate block to conditionally control which objects are generated.

Generate If... else Statement Behavioral Verilog Coding Example

In the following coding example of a generate if... else statement, generate controls the type of multiplier that is instantiated.

•The contents of each branch of the if... else statement are enclosed by begin and end statements.

•The begin statement is named with a unique qualifier.

generate

if (IF_WIDTH < 10) begin : if_name

adder # (IF_WIDTH) u1 (a, b, sum_if); end

else

begin : else_name

subtractor # (IF_WIDTH) u2 (a, b, sum_if); end

endgenerate

Behavioral Verilog Generate Case Statements

Use a generate case statement inside a generate block to conditionally control which objects are generated. Use a generate case statement when there are several conditions to be tested to determine what the generated code would be.

• Each test statement in a generate case is enclosed by begin and end statements.

•The begin statement is named with a unique qualifier.

Behavioral Verilog Generate Case Statement Coding Example

In the following coding example of a generate case statement, generate controls the type of adder that is instantiated:

generate

case (WIDTH) 1:

begin : case1_name

adder #(WIDTH*8) x1 (a, b, ci, sum_case, c0_case); end

2:

begin : case2_name

adder #(WIDTH*4) x2 (a, b, ci, sum_case, c0_case); end

default:

begin : d_case_name

adder x3 (a, b, ci, sum_case, c0_case); end

endcase endgenerate

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