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Debugging Using Write Operation in VHDL

Table 6-1: XST VHDL File Type Support (Cont’d)

Function

Package

 

 

write (line, std_ulogic)

ieee.std_logic_textio

 

 

write (line, std_ulogic_vector, boolean)

ieee.std_logic_textio

 

 

write (line, std_ulogic_vector)

ieee.std_logic_textio

 

 

write (line, std_logic_vector, boolean)

ieee.std_logic_textio

 

 

write (line, std_logic_vector)

ieee.std_logic_textio

 

 

hread

ieee.std_logic_textio

 

 

For more information on how to use a file read operation, see “Initializing RAM Coding Examples.”

Debugging Using Write Operation in VHDL

This section discusses Debugging Using Write Operation in VHDL, and includes:

“Debugging Using Write Operation in VHDL Coding Example”

“Rules for Debugging Using Write Operation in VHDL”

Debugging Using Write Operation in VHDL Coding Example

--

-- Print 2 constants to the output file

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use STD.TEXTIO.all;

use IEEE.STD_LOGIC_TEXTIO.all;

entity file_support_1 is

generic (data_width: integer:= 4); port( clk, sel: in std_logic;

din: in std_logic_vector (data_width - 1 downto 0); dout: out std_logic_vector (data_width - 1 downto 0));

end file_support_1;

architecture Behavioral of file_support_1 is file results : text is out "test.dat";

constant base_const: std_logic_vector(data_width - 1 downto 0):= conv_std_logic_vector(3,data_width);

constant new_const: std_logic_vector(data_width - 1 downto 0):= base_const + "1000";

begin

process(clk)

variable txtline : LINE; begin

write(txtline,string'("--------------------")); writeline(results, txtline); write(txtline,string'("Base Const: "));

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write(txtline,base_const); writeline(results, txtline);

write(txtline,string'("New Const: ")); write(txtline,new_const); writeline(results, txtline);

write(txtline,string'("--------------------")); writeline(results, txtline);

if (clk'event and clk='1') then if (sel = '1') then

dout <= new_const;

else

dout <= din; end if;

end if; end process;

end Behavioral;

Rules for Debugging Using Write Operation in VHDL

Follow these rules for rules for debugging using write operation in VHDL:

During a std_logic read operation, the only allowed characters are 0 and 1. Other values such as X and Z are not allowed. XST rejects the design if the file includes characters other than 0 and 1, except that XST ignores a blank space character.

Do not use identical names for files placed in different directories.

Do not use conditional calls to read procedures, as shown in the following coding example:

if SEL = '1' then

read (MY_LINE, A(3 downto 0)); else

read (MY_LINE, A(1 downto 0)); end if;

When using the endfile function, if you use the following description style:

while (not endfile (MY_FILE)) loop readline (MY_FILE, MY_LINE); read (MY_LINE, MY_DATA);

end loop;

XST rejects the design, and issues the following error message:

Line <MY_LINE> has not enough elements for target <MY_DATA>.

To fix the problem, add exit when endfile (MY_FILE); to the while loop as shown in the following coding example:

while (not endfile (MY_FILE)) loop readline (MY_FILE, MY_LINE); exit when endfile (MY_FILE); read (MY_LINE, MY_DATA);

end loop;

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