-wysiwyg {yes|no}

The default is no.

WYSIWYG Project Navigator Syntax Example

Define WYSIWYG globally in Project Navigator > Process Properties >

Xilinx-Specific Options > WYSIWYG.

XOR Preserve (–pld_xp)

XOR Preserve (-pld_xp) enables or disables hierarchical flattening of XOR macros.

The XORs inferred by Hardware Description Language (HDL) synthesis are also considered as macro blocks in the CPLD flow. They are processed separately to give more flexibility for using device macrocells XOR gates. Therefore, you can decide to flatten its design (Flatten Hierarchy yes, Macro Preserve no) but you want to preserve the XORs. Preserving XORs has a great impact on reducing design complexity.

XOR Preserve values are:

•yes (default)

XOR macros are preserved

•no

XOR macros are merged with surrounded logic

Preserving XORs generally gives better results. That is, the number of PTerms is lower. Use the no value to obtain completely flat netlists. Applying global optimization on a completely flat design sometimes improves design fitting.

To obtain a completely flattened design, select the following options:

•Flatten Hierarchy yes

•Macro Preserve no

•XOR Preserve no

The no value does not guarantee the elimination of the XOR operator from the Electronic Data Interchange Format (EDIF) netlist. During the netlist generation, the netlist mapper tries to recognize and infer XOR gates in order to decrease the logic complexity. This process is independent of the XOR preservation done by Hardware Description Language (HDL) synthesis, and is guided only by the goal of complexity reduction.

XOR Preserve Architecture Support

XOR Preserve applies to all CPLD devices. XOR Preserve does not apply to FPGA devices.

XOR Preserve Applicable Elements

XOR Preserve applies to an entire design through the XST command line.

XOR Preserve Propagation Rules

Not applicable