The integer value range is 0 to 100 when percent (%) is used or both percent (%) and pound (#) are omitted.

Slice (LUT-FF Pairs) Utilization Ratio Delta Verilog Syntax Examples

Place Slice (LUT-FF Pairs) Utilization Ratio Delta immediately before the module declaration or instantiation:

(* slice_utilization_ratio_maxmargin = "integer" *)

(* slice_utilization_ratio_maxmargin = "integer%" *)

(* slice_utilization_ratio_maxmargin = "integer#" *)

In the preceding examples, XST interprets the integer values in the first two attributes as a percentage, and in the last attribute as an absolute number of slices or FF-LUT pairs.

Slice (LUT-FF Pairs) Utilization Ratio Delta XCF Syntax Example One

MODEL "entity_name" slice_utilization_ratio_maxmargin=integer;

Slice (LUT-FF Pairs) Utilization Ratio Delta XCF Syntax Example Two

MODEL "entity_name" slice_utilization_ratio_maxmargin="integer%";

Slice (LUT-FF Pairs) Utilization Ratio Delta XCF Syntax Example Three

MODEL "entity_name" slice_utilization_ratio_maxmargin="integer#";

In the preceding examples, XST interprets the integer values in the first two lines as a percentage and in the last line as an absolute number of slices or FF-LUT pairs.

There must be no space between the integer value and the percent (%) or pound (#) characters.

You must surround the integer value and the percent (%) and pound (#) characters with double quotes ("...") because the percent (%) and pound (#) characters are special characters in the XST Constraint File (XCF).

The integer value range is 0 to 100 when percent (%) is used or both percent (%) and pound (#) are omitted.

Slice (LUT-FF Pairs) Utilization Ratio Delta XST Command Line Syntax Examples

Define Slice (LUT-FF Pairs) Utilization Ratio Delta globally with the – slice_utilization_ratio_maxmargin command line option of the run command:

-slice_utilization_ratio_maxmargin integer

-slice_utilization_ratio_maxmargin integer%

-slice_utilization_ratio_maxmargin integer#

In the preceding example, XST interprets the integer values in the first two lines as a percentage and in the last line as an absolute number of slices or FF-LUT pairs.

The integer value range is 0 to 100 when percent (%) is used or both percent (%) and pound (#) are omitted.

Map Entity on a Single LUT (LUT_MAP)

Map Entity on a Single LUT (LUT_MAP) forces XST to map a single block into a single LUT. If a described function on an RTL level description does not fit in a single LUT, XST issues an error message.

10.1

Use the UNISIM library to directly instantiate LUT components in your Hardware Description Language (HDL) code. To specify a function that a particular LUT must execute, apply an INIT constraint to the instance of the LUT. To place an instantiated LUT or register in a particular slice, attach an “RLOC” constraint to the same instance.

It is not always convenient to calculate INIT functions and different methods can be used to achieve this. Instead, you can describe the function that you want to map onto a single LUT in your VHDL or Verilog code in a separate block. Attaching a LUT_MAP constraint to this block indicates to XST that this block must be mapped on a single LUT. XST automatically calculates the INIT value for the LUT and preserves this LUT during optimization. For more information, see “Specifying INIT and RLOC.”

XST automatically recognizes the XC_MAP constraint supported by Synplicity.

Map Entity on a Single LUT Architecture Support

Map Entity on a Single LUT applies to all FPGA devices. Map Entity on a Single LUT does not apply to CPLD devices.

Map Entity on a Single LUT Applicable Elements

Map Entity on a Single LUT applies to a VHDL entity or Verilog module.

Map Entity on a Single LUT Propagation Rules

Map Entity on a Single LUT applies to the entity or module to which it is attached.

Map Entity on a Single LUT Syntax Examples

Following are syntax examples using Map Entity on a Single LUT with particular tools or methods. If a tool or method is not listed, Map Entity on a Single LUT may not be used with it.

Map Entity on a Single LUT VHDL Syntax Example

Before using Map Entity on a Single LUT, declare it with the following syntax:

attribute lut_map: string;

After declaring Map Entity on a Single LUT, specify the VHDL constraint:

attribute lut_map of entity_name : entity is "{yes|no}";

Map Entity on a Single LUT Verilog Syntax Example

Place Map Entity on a Single LUT immediately before the module declaration or instantiation:

(* lut_map = "{yes|no}" *)

Map Entity on a Single LUT XCF Syntax Example

MODEL "entity_name" lut_map={yes|no|true|false};

Use Carry Chain (USE_CARRY_CHAIN)

XST uses carry chain resources to implement certain macros, but there are situations where you can obtain better results by not using carry chain. Use Carry Chain (USE_CARRY_CHAIN) can deactivate carry chain use for macro generation. Use Carry Chain is both a global and a local constraint.

Use Carry Chain values are:

•yes (default)

•no

Use Carry Chain Architecture Support

Use Carry Chain applies to all FPGA devices. Use Carry Chain does not apply to CPLD devices.

Use Carry Chain Applicable Elements

Use Carry Chain applies globally, or to signals.

Use Carry Chain Propagation Rules

Use Carry Chain applies to the signal to which it is attached.

Use Carry Chain Syntax Examples

Following are syntax examples using Use Carry Chain with particular tools or methods. If a tool or method is not listed, Use Carry Chain may not be used with it.

Use Carry Chain Schematic Syntax Example

•Attach to a valid instance

•Attribute Name USE_CARRY_CHAIN

•Attribute Values

♦yes

♦no

Use Carry Chain VHDL Syntax Example

Before using Use Carry Chain, declare it with the following syntax:

attribute use_carry_chain: string;

After declaring Use Carry Chain specify the VHDL constraint:

attribute use_carry_chain of signal_name: signal is "{yes|no}";

Use Carry Chain Verilog Syntax Example

Place Use Carry Chain immediately before the signal declaration:

(* use_carry_chain = "{yes|no}" *)

Use Carry Chain XCF Syntax Example One

MODEL "entity_name" use_carry_chain={yes|no|true|false};

Use Carry Chain XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" use_carry_chain={yes|no|true|false};

END;

10.1

Use Carry Chain XST Command Line Syntax Example

Define Use Carry Chain globally with the –use_carry_chain command line option of the run command:

-use_carry_chain {yes|no}

The default is yes.

Convert Tristates to Logic (TRISTATE2LOGIC)

Since some devices do not support internal tristates, XST automatically replaces tristates with equivalent logic. Because the logic generated from tristates can be combined and optimized with surrounding logic, the replacement of internal tristates by logic for other devices can lead to better speed, and in some cases, better area optimization. But in general tristate to logic replacement may lead to area increase. If the optimization goal is Area, you should apply Convert Tristates to Logic (TRISTATE2LOGIC) set to no.

Convert Tristates to Logic Limitations

•Only internal tristates are replaced by logic. The tristates of the top module connected to output pads are preserved.

•Internal tristates are not replaced by logic for modules when incremental synthesis is active.

•Convert Tristates to Logic does not apply to technologies that do not have internal tristates, such as Spartan-3 or Virtex-4 devices. In this case, the conversion of tristates to logic is performed automatically. In some situations XST is unable to make the replacement automatically, due to the fact that this may lead to wrong design behavior or multi-source. This may happen when the hierarchy is preserved or XST does not have full design visibility (for example, design is synthesized on a block-by- block basis). In these cases, XST issues a warning at the low level optimization step. Depending on the particular design situation, you may continue the design flow and the replacement could be done by MAP, or you can force the replacement by applying Convert Tristates to Logic set to yes on a particular block or signal.

•The situations in which XST is unable to replace a tristate by logic are:

♦The tristate is connected to a black box.

♦The tristate is connected to the output of a block, and the hierarchy of the block is preserved.

♦The tristate is connected to a top-level output.

♦Convert Tristates to Logic is set to no on the block where tristates are placed, or on the signals to which tristates are connected.

Convert Tristates to Logic values are:

•yes (default)

•no

•true (XCF only)

•false (XCF only)

Convert Tristates to Logic Architecture Support

Convert Tristates to Logic applies to the following FPGA devices only:

•Virtex, Virtex-E

•Spartan-II, Spartan-IIE

•Virtex-II, Virtex-II Pro

Convert Tristates to Logic does not apply to CPLD devices.

Convert Tristates to Logic Applicable Elements

Convert Tristates to Logic applies to:

•An entire design through the XST command line

•A particular block (entity, architecture, component)

•A signal

Convert Tristates to Logic Propagation Rules

Convert Tristates to Logic applies to an entity, component, module or signal to which it is attached.

Convert Tristates to Logic Syntax Examples

Following are syntax examples using Convert Tristates to Logic with particular tools or methods. If a tool or method is not listed, Convert Tristates to Logic may not be used with it.

Convert Tristates to Logic VHDL Syntax Example

Before using Convert Tristates to Logic, declare it with the following syntax:

attribute tristate2logic: string;

After declaring Convert Tristates to Logic, specify the VHDL constraint:

attribute tristate2logic of {entity_name|component_name|signal_name}: {entity|component|signal} is "{yes|no}";

Convert Tristates to Logic Verilog Syntax Example

Place Convert Tristates to Logic immediately before the module or signal declaration:

(* tristate2logic = "{yes|no}" *)

Convert Tristates to Logic XCF Syntax Example One

MODEL "entity_name" tristate2logic={yes|no|true|false};

Convert Tristates to Logic XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" tristate2logic={yes|no|true|false};

END;

10.1