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Logical Shifters HDL Coding Techniques
end archi;
3-Bit 1-of-9 Priority Encoder Verilog Coding Example
//
// 3-Bit 1-of-9 Priority Encoder
//
(* priority_extract="force" *)
module v_priority_encoder_1 (sel, code);
input |
[7:0] sel; |
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output |
[2:0] |
code; |
reg |
[2:0] |
code; |
always @(sel)
begin |
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if |
(sel[0]) code = 3'b000; |
else if (sel[1]) code = 3'b001; else if (sel[2]) code = 3'b010; else if (sel[3]) code = 3'b011; else if (sel[4]) code = 3'b100; else if (sel[5]) code = 3'b101; else if (sel[6]) code = 3'b110; else if (sel[7]) code = 3'b111;
else |
code = 3'bxxx; |
end |
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endmodule |
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Logical Shifters HDL Coding Techniques
This section discusses Logical Shifters HDL Coding Techniques, and includes:
•“About Logical Shifters”
•“Logical Shifters Log File”
•“Logical Shifters Related Constraints”
•“Logical Shifters Coding Examples”
About Logical Shifters
Xilinx defines a logical shifter as a combinatorial circuit with 2 inputs and 1 output:
•The first input is a data input that is shifted.
•The second input is a selector whose binary value defines the shift distance.
•The output is the result of the shift operation.
All of these I/Os are mandatory. Otherwise, XST does not infer a logical shifter.
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Follow these rules when writing your HDL code:
•Use only logical, arithmetic and rotate shift operators. Shift operations that fill vacated positions with values from another signal are not recognized.
•For VHDL, you can use predefined shift (for example, SLL, SRL, ROL) or concatenation operations only. For more information on predefined shift operations, see the IEEE VHDL reference manual.
•Use only one type of shift operation.
•The n value in the shift operation must be incremented or decremented only by 1 for each consequent binary value of the selector.
•The n value can be positive only.
•All values of the selector must be presented.
Logical Shifters Log File
The XST log file reports the type and size of a recognized logical shifter during the Macro Recognition step.
...
Synthesizing Unit <lshift>.
Related source file is Logical_Shifters_1.vhd. Found 8-bit shifter logical left for signal <so>. Summary:
inferred 1 Combinational logic shifter(s). Unit <lshift> synthesized.
...
==============================
HDL Synthesis Report |
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Macro Statistics |
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# Logic shifters |
: 1 |
8-bit shifter logical left |
: 1 |
============================== |
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... |
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Logical Shifters Related Constraints
•“Logical Shifter Extraction (SHIFT_EXTRACT)”
Logical Shifters Coding Examples
The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.
•“Logical Shifter One”
•“Logical Shifter Two”
•“Logical Shifter Three”
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Logical Shifters HDL Coding Techniques
Logical Shifter One
This section discusses Logical Shifter One, and includes:
•“Logical Shifter One Diagram”
•“Logical Shifter One Pin Descriptions”
•“Logical Shifter One VHDL Coding Example”
•“Logical Shifter One Verilog Coding Example”
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Figure 2-36: Logical Shifter One Diagram |
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Table 2-42: Logical Shifter One Pin Descriptions |
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DI |
Data Input |
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SEL |
Shift Distance Selector |
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Data Output |
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Logical Shifter One VHDL Coding Example
--
-- Following is the VHDL code for a logical shifter.
--
library ieee;
use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity logical_shifters_1 is
port(DI : in unsigned(7 downto 0); SEL : in unsigned(1 downto 0); SO : out unsigned(7 downto 0));
end logical_shifters_1;
architecture archi of logical_shifters_1 is begin
with SEL select
SO <= DI when "00", DI sll 1 when "01", DI sll 2 when "10", DI sll 3 when others;
end archi;
XST User Guide |
www.xilinx.com |
107 |
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Chapter 2: XST HDL Coding Techniques
Logical Shifter One Verilog Coding Example
//
// Following is the Verilog code for a logical shifter.
//
module v_logical_shifters_1 (DI, SEL, SO); input [7:0] DI;
input [1:0] SEL; output [7:0] SO; reg [7:0] SO;
always @(DI or SEL) begin
case (SEL)
2'b00 : SO = DI; 2'b01 : SO = DI << 1; 2'b10 : SO = DI << 2;
default : SO = DI << 3; endcase
end endmodule
Logical Shifter Two
This section discusses Logical Shifter Two, and includes:
•“Logical Shifter Two Pin Descriptions”
•“Logical Shifter Two VHDL Coding Example”
•“Logical Shifter Two Verilog Coding Example”
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XST does not infer a logical shifter for Logical Shifter Two, since not all selector values are presented.
Table 2-43: Logical Shifter Two Pin Descriptions
IO Pins |
Description |
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DI |
Data Input |
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SEL |
Shift Distance Selector |
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SO |
Data Output |
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Logical Shifter Two VHDL Coding Example
--
--XST does not infer a logical shifter for this example,
--as not all of the selector values are presented.
--
library ieee;
use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity logical_shifters_2 is
port(DI : in unsigned(7 downto 0); SEL : in unsigned(1 downto 0); SO : out unsigned(7 downto 0));
end logical_shifters_2;
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Logical Shifters HDL Coding Techniques
architecture archi of logical_shifters_2 is begin
with SEL select
SO <= DI when "00", DI sll 1 when "01", DI sll 2 when others;
end archi;
Logical Shifter Two Verilog Coding Example
//
//XST does not infer a logical shifter for this example,
//as not all of the selector values are presented.
//
module v_logical_shifters_2 (DI, SEL, SO); input [7:0] DI;
input [1:0] SEL; output [7:0] SO; reg [7:0] SO;
always @(DI or SEL) begin
case (SEL)
2'b00 : SO = DI; 2'b01 : SO = DI << 1;
default : SO = DI << 2; endcase
end endmodule
Logical Shifter Three
This section discusses Logical Shifter Three, and includes:
•“Logical Shifter Three Pin Descriptions”
•“Logical Shifter Three VHDL Coding Example”
•“Logical Shifter Three Verilog Coding Example”
XST does not infer a logical shifter for this example, as the value is not incremented by 1 for each consequent binary value of the selector.
Table 2-44: Logical Shifter Three Pin Descriptions
IO Pins |
Description |
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DI |
Data Input |
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SEL |
Shift Distance Selector |
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SO |
Data Output |
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Logical Shifter Three VHDL Coding Example
--
--XST does not infer a logical shifter for this example,
--as the value is not incremented by 1 for each consequent
--binary value of the selector.
--
XST User Guide |
www.xilinx.com |
109 |
10.1
Chapter 2: XST HDL Coding Techniques
R
library ieee;
use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity logical_shifters_3 is
port(DI : in unsigned(7 downto 0); SEL : in unsigned(1 downto 0); SO : out unsigned(7 downto 0));
end logical_shifters_3;
architecture archi of logical_shifters_3 is begin
with SEL select
SO <= DI when "00", DI sll 1 when "01", DI sll 3 when "10", DI sll 2 when others;
end archi;
Logical Shifter Three Verilog Coding Example
//
//XST does not infer a logical shifter for this example,
//as the value is not incremented by 1 for each consequent
//binary value of the selector.
//
module v_logical_shifters_3 (DI, SEL, SO); input [7:0] DI;
input [1:0] SEL; output [7:0] SO; reg[7:0] SO;
always @(DI or SEL) begin
case (SEL)
2'b00 : SO = DI; 2'b01 : SO = DI << 1; 2'b10 : SO = DI << 3;
default : SO = DI << 2; endcase
end endmodule
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XST User Guide |
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