Resource Sharing (RESOURCE_SHARING)

Resource Sharing (RESOURCE_SHARING) enables or disables resource sharing of arithmetic operators.

Resource Sharing values are:

•yes (default)

•no

•force

•true (XCF only)

•false (XCF only)

Resource Sharing Architecture Support

Resource Sharing is architecture independent.

Resource Sharing Applicable Elements

Resource Sharing applies globally, or to design elements.

Resource Sharing Propagation Rules

Resource Sharing applies to the entity or module to which it is attached.

Resource Sharing Syntax Examples

Following are syntax examples using Resource Sharing with particular tools or methods. If a tool or method is not listed, Resource Sharing may not be used with it.

Resource Sharing VHDL Syntax Example

Before using Resource Sharing declare it with the following syntax:

attribute resource_sharing: string;

After declaring Resource Sharing, specify the VHDL constraint:

attribute resource_sharing of entity_name: entity is "{yes|no}";

Resource Sharing Verilog Syntax Example

Place Resource Sharing immediately before the module declaration or instantiation:

(* resource_sharing = "{yes|no}" *)

Resource Sharing XCF Syntax Example One

MODEL "entity_name" resource_sharing={yes|no|true|false};

Resource Sharing XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" resource_sharing={yes|no|true|false};

END;

Resource Sharing XST Command Line Syntax Example

Define Resource Sharing globally with the -resource_sharing command line option of the run command:

-resource_sharing {yes|no}

The default is yes.

Resource Sharing Project Navigator Syntax Example

Define Resource Sharing globally in Project Navigator > HDL Options >

Resource Sharing.

Safe Recovery State (SAFE_RECOVERY_STATE)

Safe Recovery State (SAFE_RECOVERY_STATE) defines a recovery state for use when a finite state machine (FSM) is implemented in Safe Implementation mode. If the FSM enters an invalid state, XST uses additional logic to force the FSM to a valid recovery state. By implementing FSM in safe mode, XST collects all code not participating in the normal FSM behavior and treats it as illegal.

XST uses logic that returns the FSM synchronously to the:

•Known state

•Reset state

•Power up state

•State you specified using SAFE_RECOVERY_STATE

For more information, see “Safe Implementation (SAFE_IMPLEMENTATION).”

Safe Recovery State Architecture Support

Safe Recovery State is architecture independent.

Safe Recovery State Applicable Elements

Safe Recovery State applies to a signal representing a state register.

Safe Recovery State Propagation Rules

Safe Recovery State applies to a signal to which it is attached.

Safe Recovery State Syntax Examples

Following are syntax examples using Safe Recovery State with particular tools or methods. If a tool or method is not listed, Safe Recovery State may not be used with it.

Safe Recovery State VHDL Syntax Example

Before using Safe Recovery State, declare it with the following syntax:

attribute safe_recovery_state: string;

After declaring Safe Recovery State, specify the VHDL constraint:

attribute safe_recovery_state of {signal_name}:{signal} is "<value>";

10.1

Safe Implementation (SAFE_IMPLEMENTATION)

Safe Implementation (SAFE_IMPLEMENTATION) implements finite state machines (FSMs) in Safe Implementation mode. In Safe Implementation mode, XST generates additional logic that forces an FSM to a valid state (recovery state) if the FSM enters an invalid state. By default, XST automatically selects reset as the recovery state. If the FSM does not have an initialization signal, XST selects power-up as the recovery state.

Define the recovery state manually with “Safe Recovery State (SAFE_RECOVERY_STATE).”

To activate Safe Implementation in:

•Project Navigator

Select Project Navigator > Process Properties > HDL Options > Safe Implementation.

•HDL

Apply Safe Implementation (SAFE_IMPLEMENTATION) to the hierarchical block or signal that represents the state register in the FSM.

Safe Implementation Architecture Support

Safe Implementation is architecture independent.

Safe Implementation Applicable Elements

Safe Implementation applies to an entire design through the XST command line, to a particular block (entity, architecture, component), or to a signal.

Safe Implementation Propagation Rules

Safe Implementation applies to an entity, component, module, or signal to which it is attached.

Safe Implementation Syntax Examples

Following are syntax examples using Safe Implementation with particular tools or methods. If a tool or method is not listed, Safe Implementation, may not be used with it.

Safe Implementation VHDL Syntax Example

Before using Safe Implementation, declare it with the following syntax:

attribute safe_implementation: string;

After declaring Safe Implementation, specify the VHDL constraint:

attribute safe_implementation of {entity_name|component_name|signal_name}: {entity|component|signal} is "{yes|no}";

Safe Implementation Verilog Syntax Example

Place Safe Implementation immediately before the module or signal declaration:

(* safe_implementation = "{yes|no}" *)

Safe Implementation XCF Syntax Example One

MODEL "entity_name" safe_implementation={yes|no|true|false};

Safe Implementation XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" safe_implementation={yes|no|true|false};

END;

Safe Implementation XST Command Line Syntax Example

Define Safe Implementation globally with the –safe_implementation command line option of the run command:

-safe_implementation {yes|no}

The default is no.

Safe Implementation Project Navigator Syntax Example

Define Safe Implementation globally in Project Navigator > HDL Options >Safe Implementation.

Signal Encoding (SIGNAL_ENCODING)

Signal Encoding (SIGNAL_ENCODING) selects the coding technique to use for internal signals.

Signal Encoding values are:

•auto

The default. The best coding technique is automatically selected for each individual signal.

•one-hot

Forces the encoding to a one-hot encoding

•user

Forces XST to keep your encoding

Signal Encoding Architecture Support

Signal Encoding is architecture independent.

Signal Encoding Applicable Elements

Signal Encoding applies globally, or to a VHDL entity, Verilog module, or signal.

10.1