Behavioral Verilog Module Declarations

Behavioral Verilog Module Declarations

This section discusses Behavioral Verilog Module Declarations, and includes:

•“About Behavioral Verilog Module Declarations”

•“Behavioral Verilog Module Declaration Coding Examples”

About Behavioral Verilog Module Declarations

The I/O ports of the circuit are declared in the module declaration. Each port has:

•A name

•A mode (in, out, and inout)

The input and output ports defined in the module declaration called EXAMPLE are the basic input and output I/O signals for the design. The inout port in Verilog is analogous to a bi-directional I/O pin on the device with the data flow for output versus input being controlled by the enable signal to the tristate buffer.

The “Behavioral Verilog Module Declaration Coding Example” describes E as a tristate buffer with a high-true output enable signal.

•If oe = 1, the value of signal A is output on the pin represented by E.

•If oe = 0, the buffer is in high impedance (Z), and any input value driven on the pin E (from the external logic) is brought into the device and fed to the signal represented by D.

Behavioral Verilog Module Declaration Coding Examples

This section gives the following Behavioral Verilog Module Declaration coding examples:

•“Behavioral Verilog Module Declaration Coding Example”

Behavioral Verilog Module Declaration Coding Example

module EXAMPLE (A, B, C, D, E); input A, B, C;

output D; inout E; wire D, E;

...

assign E = oe ? A : 1’bz; assign D = B & E;

...

endmodule

Behavioral Verilog Continuous Assignments

This section discusses Behavioral Verilog Continuous Assignments, and includes:

•“About Behavioral Verilog Continuous Assignments”

•“Behavioral Verilog Continuous Assignments Coding Examples”

About Behavioral Verilog Continuous Assignments

Continuous assignments are used to model combinatorial logic in a concise way. Both explicit and implicit continuous assignments are supported. Explicit continuous

10.1