An error occurs if a leading space is inadvertently entered in the value field. From ISE 8.1i Service Pack 1 forward, Project Navigator automatically strips leading spaces from a process value. Accordingly, the .xst file written by Project Navigator is not affected by leading spaces. If you hand-edit the .xst file and run XST from the command line, manually delete any leading spaces.

For the previous command example, stopwatch.xst should look like the following:

run

-ifn watchvhd.prj -ifmt mixed

-top stopwatch -ofn watchvhd.ngc -ofmt NGC

-p xcv50-bg256-6 -opt_mode Speed -opt_level 1

Synthesizing Verilog Designs Using Command Line Mode

This section discusses Synthesizing Verilog Designs Using command line mode, and includes:

•“Synthesizing Verilog Designs Using Command Line Mode (Example)”

•“Running XST in Script Mode (Verilog)”

Synthesizing Verilog Designs Using Command Line Mode (Example)

This example shows the synthesis of a hierarchical Verilog design for a Virtex FPGA using command line mode.

The following coding example uses a Verilog design, called watchver. These files are found in the ISEexamples\watchver directory of the ISE installation directory.

•stopwatch.v

•statmach.v

•decode.v

•cnt60.v

•smallcntr.v

•tenths.v

•hex2led.v

This design contains seven modules:

•stopwatch

•statmach

•tenths (a CORE Generator™ core)

•decode

•cnt60

•smallcntr

•hex2led

For the example, perform the following steps:

1.Create a new directory named vlg_m.

2.Copy the watchver design files from the ISEexamples\watchver directory of the ISE installation directory to the newly created vlg_m directory.

Specify the top-level design block with the -top command line option.

To synthesize the design, which is now represented by seven Verilog files, create a project. XST now supports mixed VHDL and Verilog projects. Therefore, Xilinx recommends that you use the new project format whether it is a real mixed language project or not. In this example, we use the new project format. To create a project file containing only Verilog files, place a list of Verilog files preceded by the keyword verilog in a separate file. The order of the files is not important. XST can recognize the hierarchy and compile Verilog files in the correct order.

For our example:

1.Open a new file, called watchver.v.

2.Enter the names of the Verilog files into this file in any order and save it:

verilog work decode.v verilog work statmach.v verilog work stopwatch.v verilog work cnt60.v verilog work smallcntr.v verilog work hex2led.v

3.To synthesize the design, execute the following command from the XST shell or a script file:

run -ifn watchver.v -ifmt mixed -top stopwatch -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6 -opt_mode Speed -opt_level 1

To synthesize just HEX2LED and check its performance independently of the other blocks, specify the top-level module to synthesize in the command line, using the -top option. For more information, see Table 5-1, page 318.

run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6 -opt_mode Speed -opt_level 1 -top HEX2LED

Running XST in Script Mode (Verilog)

It can be tedious to enter XST commands directly into the XST shell, especially when you have to specify several options and execute the same command several times.

To run XST in script mode:

1.Open a new file called design.xst in the current directory. Put the previously executed XST shell command into this file and save it.

run -ifn watchver.prj -ifmt mixed -ofn watchver.ngc

-ofmt NGC -p xcv50-bg256-6 -opt_mode Speed -opt_level 1

2.From the tcsh or other shell, enter the following command to begin synthesis. xst -ifn design.xst

10.1