Tristates HDL Coding Techniques

Q <= D; end if;

end process; end archi;

4-Bit Latch With Inverted Gate and Asynchronous Set Verilog Coding Example

//

// 4-bit Latch with Inverted Gate and Asynchronous Set

//

module v_latches_3 (G, D, PRE, Q); input G, PRE;

input [3:0] D; output [3:0] Q; reg [3:0] Q;

always @(G or D or PRE) begin

if (PRE)

Q = 4'b1111; else if (~G)

Q = D;

end endmodule

Tristates HDL Coding Techniques

This section discusses Tristates HDL Coding Techniques, and includes:

•“About Tristates”

•“Tristates Log File”

•“Tristates Related Constraints”

•“Tristates Coding Examples”

About Tristates

Tristate elements can be described using:

•Combinatorial process (VHDL) and always block (Verilog)

•Concurrent assignment

In the “Tristates Coding Examples,” comparing to 0 instead of 1 infers a BUFT primitive instead of a BUFE macro. The BUFE macro has an inverter on the E pin.

Tristates Log File

The XST log file reports the type and size of recognized tristates during the Macro

Recognition step.

...

Synthesizing Unit <three_st>.

Related source file is tristates_1.vhd. Found 1-bit tristate buffer for signal <o>. Summary:

10.1

inferred 1 Tristate(s). Unit <three_st> synthesized.

=============================

Tristates Related Constraints

•“Convert Tristates to Logic (TRISTATE2LOGIC)”

Tristates Coding Examples

This section gives the following Tristate examples:

•“Tristate Description Using Combinatorial Process and Always Block”

•“Tristate Description Using Concurrent Assignment”

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

Tristate Description Using Combinatorial Process and Always Block

This section discusses Tristate Description Using Combinatorial Process and Always

Block, and includes:

•“Tristate Description Using Combinatorial Process and Always Block Diagram”

•“Tristate Description Using Combinatorial Process and Always Block Pin Descriptions”

•“Tristate Description Using Combinatorial Process VHDL Coding Example”

•“Tristate Description Using Combinatorial Always Block Verilog Coding Example”

BUFT

T

Figure 2-9: Tristate Description Using Combinatorial Process and Always Block Diagram

Table 2-11: Tristate Description Using Combinatorial Process and Always Block Pin

Descriptions

Tristate Description Using Combinatorial Process VHDL Coding Example

--

-- Tristate Description Using Combinatorial Process

--

library ieee;

use ieee.std_logic_1164.all;

entity three_st_1 is port(T : in std_logic;

I : in std_logic; O : out std_logic);

end three_st_1;

architecture archi of three_st_1 is begin

process (I, T) begin

if (T='0') then O <= I;

else

O <= 'Z'; end if;

end process;

end archi;

Tristate Description Using Combinatorial Always Block Verilog Coding Example

//

// Tristate Description Using Combinatorial Always Block

//

module v_three_st_1 (T, I, O); input T, I;

output O; reg O;

always @(T or I) begin

if (~T)

O = I; else

O = 1'bZ;

end

endmodule

10.1

Tristate Description Using Concurrent Assignment

This section discusses Tristate Description Using Concurrent Assignment, and includes:

•“Tristate Description Using Concurrent Assignment Diagram”

•“Tristate Description Using Concurrent Assignment Pin Descriptions”

•“Tristate Description Using Concurrent Assignment VHDL Coding Example”

•“Tristate Description Using Concurrent Assignment Verilog Coding Example”

T

Figure 2-10: Tristate Description Using Concurrent Assignment Diagram

Table 2-12: Tristate Description Using Concurrent Assignment Pin Descriptions

Tristate Description Using Concurrent Assignment VHDL Coding Example

--

-- Tristate Description Using Concurrent Assignment

--

library ieee;

use ieee.std_logic_1164.all;

entity three_st_2 is port(T : in std_logic;

I : in std_logic; O : out std_logic);

end three_st_2;

architecture archi of three_st_2 is begin

O <= I when (T='0') else 'Z'; end archi;

Tristate Description Using Concurrent Assignment Verilog Coding Example

//

// Tristate Description Using Concurrent Assignment

//

module v_three_st_2 (T, I, O);