Multipliers HDL Coding Techniques

Unsigned 8-Bit Greater or Equal Comparator VHDL Coding Example

--

-- Unsigned 8-bit Greater or Equal Comparator

--

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity comparator_1 is

port(A,B : in std_logic_vector(7 downto 0); CMP : out std_logic);

end comparator_1;

architecture archi of comparator_1 is begin

CMP <= '1' when A >= B else '0';

end archi;

Unsigned 8-Bit Greater or Equal Comparator Verilog Coding Example

//

// Unsigned 8-bit Greater or Equal Comparator

//

module v_comparator_1 (A, B, CMP); input [7:0] A;

input [7:0] B; output CMP;

assign CMP = (A >= B) ? 1'b1 : 1'b0;

endmodule

Multipliers HDL Coding Techniques

This section discusses Multipliers and HDL Coding Techniques, and includes:

•“About Multipliers”

•“Large Multipliers Using Block Multipliers”

•“Registered Multipliers”

•“Multipliers (Virtex-4, Virtex-5, and Spartan-3A D Devices)”

•“Multiplication with Constant”

•“Multipliers Log File”

•“Multipliers Related Constraints”

•“Multipliers Coding Examples”

10.1

About Multipliers

When implementing a multiplier, the size of the resulting signal is equal to the sum of 2 operand lengths. If you multiply A (8-bit signal) by B (4-bit signal), then the size of the result must be declared as a 12-bit signal.

Large Multipliers Using Block Multipliers

XST can generate large multipliers using an 18x18 bit block multiplier in the following devices:

•Virtex-II

•Virtex-II Pro

For multipliers larger than this, XST can generate larger multipliers using multiple 18x18 bit block multipliers.

Registered Multipliers

In instances where a multiplier would have a registered output, XST infers a unique registered multiplier for the following devices:

•Virtex-II

•Virtex-II Pro

•Virtex-4

•Virtex-5

This registered multiplier is 18x18 bits.

Under the following conditions, a registered multiplier is not used, and a multiplier + register is used instead.

•Output from the multiplier goes to any component other than the register.

•The “Multiplier Style (MULT_STYLE)” constraint is set to lut.

•The multiplier is asynchronous.

•The multiplier has control signals other than synchronous reset or clock enable.

•The multiplier does not fit in a single 18x18 bit block multiplier.

The following pins are optional for a registered multiplier.

•Clock enable port

•Synchronous and asynchronous reset, and load ports

Multipliers (Virtex-4, Virtex-5, and Spartan-3A D Devices)

The Virtex-4, Virtex-5, and Spartan-3A D families allow multipliers to be implemented on DSP48 resources. XST supports the registered version of these macros and can push up to 2 levels of input registers and 2 levels of output registers into DSP48 blocks.

If a multiplier implementation requires multiple DSP48 resources, XST automatically decomposes it onto multiple DSP48 blocks. Depending on the operand size, and to obtain the best performance, XST may implement most of a multiplier using DSP48 blocks, and use slice logic for the rest of the macro. For example, it is not sufficient to use a single DSP48 to implement an 18x18 unsigned multiplier. In this case, XST implements most of the logic in one DSP48, and the rest in LUTs.

For Virtex-4, Virtex-5, and Spartan-3A D devices, XST can infer pipelined multipliers, not only for the LUT implementation, but for the DSP48 implementation as well. For more information, see “XST Limitations.”

Macro implementation on DSP48 blocks is controlled by the “Use DSP48 (USE_DSP48)” constraint or command line option, with a default value of auto. In this mode, XST implements multipliers taking into account available DSP48 resources in the device.

In auto mode, use “DSP Utilization Ratio (DSP_UTILIZATION_RATIO)” to control DSP48 resources for the synthesis. By default, XST tries to utilize all DSP48 resources. For more information, see “DSP48 Block Resources.”

XST can automatically recognize the “Multiplier Style (MULT_STYLE)” constraint with values lut and block and then convert internally to “Use DSP48 (USE_DSP48)”. Xilinx recommends using the “Use DSP48 (USE_DSP48)” constraint for Virtex-4 and Virtex-5 designs to define FPGA resources used for multiplier implementation. Xilinx recommends using the “Multiplier Style (MULT_STYLE)” constraint to define the multiplier implementation method on the selected FPGA resources. If “Use DSP48 (USE_DSP48)” is set to auto or yes, you may use mult_style=pipe_block to pipeline the DSP48 implementation if the multiplier implementation requires multiple DSP48 blocks. If “Use DSP48 (USE_DSP48)” is set to no, use mult_style=pipe_lut|KCM|CSD to define the multiplier implementation method on LUTs.

To deliver the best performance, XST by default tries to infer and implement the maximum macro configuration, including as many registers in the DSP48 as possible. To shape a macro in a specific way, use the “Keep (KEEP)” constraint. For example, to exclude the first register stage from the DSP48, place “Keep (KEEP)” constraints on the outputs of these registers.

Multiplication with Constant

When one of the arguments is a constant, XST can create efficient dedicated implementations of a multiplier with a constant using two methods:

•Constant Coefficient Multiplier (KCM)

•Canonical Signed Digit (CSD)

Dedicated implementations do not always provide the best results for multiplication with constants. XST can automatically choose between KCM or standard multiplier implementation. The CSD method cannot be automatically chosen. Use the “Mux Style (MUX_STYLE)” constraint to force CSD implementation.

XST does not support KCM or CSD implementation for signed numbers.

If the either of the arguments is larger than 32 bits, XST does not use KCM or CSD implementation, even if it is specified with the “Multiplier Style (MULT_STYLE)” constraint.

Multipliers Log File

The XST log file reports the type and size of recognized multipliers during the Macro

Recognition step.

...

Synthesizing Unit <mult>.

Related source file is multipliers_1.vhd. Found 8x4-bit multiplier for signal <res>. Summary:

10.1

inferred 1 Multiplier(s). Unit <mult> synthesized.

==============================

Multipliers Related Constraints

•“Multiplier Style (MULT_STYLE)”

•“Use DSP48 (USE_DSP48)”

•“DSP Utilization Ratio (DSP_UTILIZATION_RATIO)”

•“Keep (KEEP)”

Multipliers Coding Examples

The coding examples in this section are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

•“Unsigned 8x4-Bit Multiplier”

Unsigned 8x4-Bit Multiplier

This section discusses Unsigned 8x4-Bit Multiplier, and includes:

•“Unsigned 8x4-Bit Multiplier Diagram”

•“Unsigned 8x4-Bit Multiplier Pin Descriptions”

•“Unsigned 8x4-Bit Multiplier VHDL Coding Example”

•“Unsigned 8x4-Bit Multiplier Verilog Coding Example”

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