Max Fanout (MAX_FANOUT)

Max Fanout (MAX_FANOUT) limits the fanout of nets or signals. The value is an integer. Default values are shown in Table 5-4, “Max Fanout Default Values.” Max Fanout is both a global and a local constraint.

Table 5-4: Max Fanout Default Values

Large fanouts can cause routability problems. XST tries to limit fanout by duplicating gates or by inserting buffers. This limit is not a technology limit but a guide to XST. It may happen that this limit is not exactly respected, especially when this limit is small (less than 30).

In most cases, fanout control is performed by duplicating the gate driving the net with a large fanout. If the duplication cannot be performed, buffers are inserted. These buffers are protected against logic trimming at the implementation level by defining a “Keep (KEEP)” attribute in the NGC file.

If the register replication option is set to no, only buffers are used to control fanout of flipflops and latches.

Max Fanout is global for the design, but you can control maximum fanout independently for each entity or module or for given individual signals by using constraints.

If the actual net fanout is less than the Max Fanout value, XST behavior depends on how Max Fanout is specified.

•If the value of Max Fanout is set in Project Navigator, in the command line, or is attached to a specific hierarchical block, XST interprets its value as a guidance.

•If Max Fanout is attached to a specific net, XST does not perform logic replication. Putting Max Fanout on the net may prevent XST from having better timing optimization.

For example, suppose that the critical path goes through the net, which actual fanout is 80 and set Max Fanout value to 100. If Max Fanout is specified in Project Navigator, XST may replicate it, trying to improve timing. If Max Fanout is attached to the net itself, XST does not perform logic replication.

Max Fanout Architecture Support

Max Fanout applies to all FPGA devices. Max Fanout does not apply to CPLD devices.

Max Fanout Applicable Elements

Max Fanout applies globally, or to a VHDL entity, a Verilog module, or signal.

Max Fanout Propagation Rules

Max Fanout applies to the entity, module, or signal to which it is attached.

Max Fanout Syntax Examples

Following are syntax examples using Max Fanout with particular tools or methods. If a tool or method is not listed, Max Fanout may not be used with it.

Max Fanout VHDL Syntax Example

Before using Max Fanout, declare it with the following syntax:

attribute max_fanout: string;

After declaring Max Fanout, specify the VHDL constraint:

attribute max_fanout of {signal_name|entity_name}: {signal|entity} is "integer";

Max Fanout Verilog Syntax Example

Place Max Fanout immediately before the module or signal declaration:

(* max_fanout = "integer" *)

Max Fanout XCF Syntax Example One

MODEL "entity_name" max_fanout=integer;

Max Fanout XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "signal_name" max_fanout=integer;

END;

Max Fanout XST Command Line Syntax Example

Define Max Fanout globally with the -max_fanout command line option of the run command:

-max_fanout integer

Max Fanout Project Navigator Syntax Example

Define globally in Project Navigator > Process Properties > Xilinx-

Specific Options > Max Fanout.

Move First Stage (MOVE_FIRST_STAGE)

Move First Stage (MOVE_FIRST_STAGE) controls the retiming of registers with paths coming from primary inputs. Both Move First Stage constraint and “Move Last Stage (MOVE_LAST_STAGE)” relate to Register Balancing.

10.1

•A flip-flop (FF in the diagram) belongs to the First Stage if it is on the paths coming from primary inputs.

•A flip-flop belongs to the Last Stage if it is on the paths going to primary outputs.

X9564

Figure 5-2: Move First Stage

During register balancing:

•First Stage flip-flops are moved forward

•Last Stage flip-flops are moved backward.

This process can dramatically increase input-to-clock and clock-to-output timing, which is not desirable. To prevent this, you may use OFFSET_IN_BEFORE and OFFSET_IN_AFTER constraints.

In the case:

•The design does not have a strong requirements, or

•You want to see the first results without touching the first and last flip-flop stages.

Two additional constraints can be used: MOVE_FIRST_STAGE and MOVE_LAST_STAGE. Both constraints may have two values: yes and no.

•MOVE_FIRST_STAGE=no prevents the first flip-flop stage from moving

•MOVE_LAST_STAGE=no prevents the last flip-flop stage from moving

Several constraints influence register balancing. For more information, see “Register

Balancing (REGISTER_BALANCING).”

Move First Stage Architecture Support

Move First Stage applies to all FPGA devices. Move First Stage does not apply to CPLD devices.

10.1

Move First Stage Applicable Elements

Move First Stage applies to the following only:

•Entire design

•Single modules or entities

•Primary clock signal

Move First Stage Propagation Rules

For Move First Stage propagation rules, see “Move First Stage (MOVE_FIRST_STAGE).”

Move First Stage Syntax Examples

Following are syntax examples using Move First Stage with particular tools or methods. If a tool or method is not listed, Move First Stage may not be used with it.

Move First Stage VHDL Syntax Example

Before using Move First Stage, declare it with the following syntax:

attribute move_first_stage : string;

After declaring Move First Stage, specify the VHDL constraint:

attribute move_first_stage of {entity_name|signal_name}: {signal|entity} is "{yes|no}";

Move First Stage Verilog Syntax Example

Place Move First Stage immediately before the module or signal declaration:

(* move_first_stage = "{yes|no}" *)

Move First Stage XCF Syntax Example One

MODEL "entity_name" move_first_stage={yes|no|true|false};

Move First Stage XCF Syntax Example Two

BEGIN MODEL "entity_name"

NET "primary_clock_signal" move_first_stage={yes|no|true|false};

END;

Move First Stage XST Command Line Syntax Example

Define Move First Stage globally with the –move_first_stage command line option of the run command:

-move_first_stage {yes|no}

The default is yes.

Move First Stage Project Navigator Syntax Example

Define Move First Stage globally in Project Navigator > Process Properties > Xilinx-Specific Options > Move First Flip-Flop Stage.

10.1