Full Case Project Navigator Syntax Example

For Verilog files only, define Full Case globally in Project Navigator > Process Properties > Synthesis Options > Full Case.

For Case Implementation Style, select Full as a Value.

Generate RTL Schematic (–rtlview)

Generate RTL Schematic (-rtlview) enables XST to generate a netlist file, representing an RTL structure of the design. This netlist can be viewed by the RTL and Technology Viewers. Generate RTL Schematic has three possible values:

•yes

•no

•only

When only is specified, XST stops synthesis just after the RTL view is generated. The file containing the RTL view has an NGR file extension.

Generate RTL Schematic Architecture Support

Generate RTL Schematic is architecture independent.

Generate RTL Schematic Applicable Elements

Generate RTL Schematic applies to files.

Generate RTL Schematic Propagation Rules

Not applicable

Generate RTL Schematic Syntax Examples

Following are syntax examples using Generate RTL Schematic with particular tools or methods. If a tool or method is not listed, Generate RTL Schematic may not be used with it.

Generate RTL Schematic XST Command Line Syntax Example

Define Generate RTL Schematic globally with the –rtlview command line option of the run command:

-rtlview {yes|no|only}

The default is no.

Generate RTL Schematic Project Navigator Syntax Example

Define Generate RTL Schematic globally in Project Navigator > Process

Properties > Synthesis Options > Generate RTL Schematic.

The default is yes.

Generics (-generics)

Generics (-generics) allows you to to redefine generics (VHDL) or parameters (Verilog) values defined in the top-level design block. This allows you to easily modify the design configuration without any Hardware Description Language (HDL) source modifications, such as for IP core generation and testing flows. If the defined value does not correspond

to the data type defined in the VHDL or Verilog code, then XST tries to detect the situation and issues a warning, ignoring the command line definition.

In some situations, XST may fail to detect a type mismatch. In that case, XST attempts to apply this value by adopting it to the type defined in the VHDL or Verilog file without any warning. Be sure that the value you specified corresponds to the type defined in the VHDL or Verilog code. If a defined generic or parameter name does not exist in the design, no message is given, and the definition is ignored.

Generics Architecture Support

Generics is architecture independent.

Generics Applicable Elements

Generics applies to the entire design.

Generics Propagation Rules

Not applicable

Generics Syntax Examples

Following are syntax examples using Generics with particular tools or methods. If a tool or method is not listed, Generics may not be used with it.

Generics XST Command Line Syntax Example

Define Generics globally with the -generics command line option of the run command:

-generics {name=value name=value .}

where

name

is the name of a generic or parameter of the top level design block, and

value

is the value of a generic or parameter of the top level design block.

The default is an empty definition:

-generics {}

Follow these rules:

•Place the values inside curly braces ({...}).

•Separate the values with spaces.

•XST can accept as values only constants of scalar types. Composite data types (arrays or records) are supported only in the following situations:

♦string

♦std_logic_vector

♦std_ulogic_vector

♦signed, unsigned

♦bit_vector

10.1

•There are no spaces between the prefix and the corresponding value:

-generics {company="Xilinx" width=5 init_vector=b100101}

Generics Project Navigator Syntax Example

Define Generics globally in Project Navigator > Process Properties >

Synthesis Options > Generics, Parameters.

Do not use curly braces ({...}) when specifying values in Project Navigator:

company="Xilinx" width=5 init_vector=b100101

Hierarchy Separator (–hierarchy_separator)

Hierarchy Separator (-hierarchy_separator) defines the hierarchy separator character that is used in name generation when the design hierarchy is flattened.

The two supported characters are:

•_ (underscore)

•/ (forward slash)

The default is / (forward slash) for newly created projects.

If a design contains a sub-block with instance INST1, and this sub-block contains a net called TMP_NET, then the hierarchy is flattened and the hierarchy separator character is / (forward slash). The name TMP_NET becomes INST1_TMP_NET. If the hierarchy separator character is / (forward slash), the net name is NST1/TMP_NET.

Using / (forward slash) as a hierarchy separator is useful in design debugging because the / (forward slash) separator makes it much easier to identify a name if it is hierarchical.

Hierarchy Separator Architecture Support

Hierarchy Separator is architecture independent.

Hierarchy Separator Applicable Elements

Hierarchy Separator applies to files.

Hierarchy Separator Propagation Rules

Not applicable

Hierarchy Separator Syntax Examples

Following are syntax examples using Hierarchy Separator with particular tools or methods. If a tool or method is not listed, Hierarchy Separator may not be used with it.

Hierarchy Separator XST Command Line Syntax Example

Define Hierarchy Separator globally with the –hierarchy_separator command line option of the run command:

-hierarchy_separator {_|/}

The default is / (forward slash) for newly created projects.

Hierarchy Separator Project Navigator Syntax Example

Define Hierarchy Separator globally in Project Navigator > Process Properties > Synthesis Options > Hierarchy Separator.

The default is / (forward slash).

I/O Standard (IOSTANDARD)

Use I/O Standard (IOSTANDARD) to assign an I/O standard to an I/O primitive. For more information, see “IOSTANDARD” in the Xilinx Constraints Guide.

Keep (KEEP)

Keep (KEEP) is an advanced mapping constraint. When a design is mapped, some nets may be absorbed into logic blocks. When a net is absorbed into a block, it can no longer be seen in the physical design database. This may happen, for example, if the components connected to each side of a net are mapped into the same logic block. The net may then be absorbed into the block containing the components. KEEP prevents this from happening.

KEEP preserves the existence of the signal in the final netlist, but not its structure. For example, if your design has a 2-bit multiplexer selector and you attach KEEP to it, this signal is preserved in the final netlist. But the multiplexer could be automatically reencoded by XST using one-hot encoding. As a consequence, this signal in the final netlist is four bits wide instead of the original two. To preserve the structure of the signal, in addition to KEEP, you must also use “Enumerated Encoding (ENUM_ENCODING)”

For more information, see “KEEP” in the Xilinx Constraints Guide.

Keep Hierarchy (KEEP_HIERARCHY)

Keep Hierarchy (KEEP_HIERARCHY) is a synthesis and implementation constraint. If hierarchy is maintained during synthesis, the implementation tools use Keep Hierarchy to preserve the hierarchy throughout implementation, and allow a simulation netlist to be created with the desired hierarchy.

XST can flatten the design to obtain better results by optimizing entity or module boundaries. You can set Keep Hierarchy to true so that the generated netlist is hierarchical and respects the hierarchy and interface of any entity or module in your design.

Keep Hierarchy is related to the hierarchical blocks (VHDL entities, Verilog modules) specified in the Hardware Description Language (HDL) design, and does not concern the macros inferred by the HDL synthesizer.

Keep Hierarchy Values

Keep Hierarchy values are:

•true

Allows the preservation of the design hierarchy, as described in the HDL project. If this value is applied to synthesis, it is also propagated to implementation. For CPLD devices, the default is true.

•false

Hierarchical blocks are merged in the top level module. For FPGA devices, the default is false.

10.1

•soft

Allows the preservation of the design hierarchy in synthesis, but KEEP_HIERARCHY is not propagated to implementation.

Preserving the Hierarchy

In general, a Hardware Description Language (HDL) design is a collection of hierarchical blocks. Preserving the hierarchy gives the advantage of fast processing because the optimization is done on separate pieces of reduced complexity. Nevertheless, very often, merging the hierarchy blocks improves the fitting results (fewer PTerms and device macrocells, better frequency) because the optimization processes (collapsing, factorization) are applied globally on the entire logic.

Keep Hierarchy Diagram

In Figure 5-1, “Keep Hierarchy Diagram,” if Keep Hierarchy is set to the entity or module I2, the hierarchy of I2 is in the final netlist, but its contents I4, I5 are flattened inside I2. I1, I3, I6, and I7 are also flattened.

X9542

Figure 5-1: Keep Hierarchy Diagram

Keep Hierarchy Architecture Support

Keep Hierarchy is architecture independent.

Keep Hierarchy Applicable Elements

Keep Hierarchy applies to logical blocks, including blocks of hierarchy or symbols.

Keep Hierarchy Propagation Rules

Keep Hierarchy applies to the entity or module to which it is attached.