Behavioral Verilog Constants

As the name implies, these types of assignments block the current process from continuing to execute additional statements at the same time. These should mainly be used in simulation.

Non-blocking assignments, on the other hand, evaluate the expression when the statement executes, but allow other statements in the same process to execute as well at the same time. The variable change occurs only after the specified delay.

Behavioral Verilog Non-Blocking Procedural Assignment Syntax Example

The syntax for a non-blocking procedural assignment is shown in the following coding example:

variable <= @(posedge_or_negedge_bit) expression;

Behavioral Verilog Non-Blocking Procedural Assignment Example

The following shows an example of how to use a non-blocking procedural assignment:

if (in1) out <= 1'b1; else out <= in2;

Behavioral Verilog Constants

By default, constants in Verilog are assumed to be decimal integers. They can be specified explicitly in binary, octal, decimal, or hexadecimal by prefacing them with the appropriate syntax. For example, the following all represent the same value:

•4'b1010

•4'o12

•4'd10

•4'ha

Behavioral Verilog Macros

Verilog provides a way to define macros as shown in the following coding example:

`define TESTEQ1 4'b1101

Later in the design code a reference to the defined macro is made as follows:

if (request == `TESTEQ1)

This is shown in the following coding example:

`define myzero 0 assign mysig = `myzero;

The Verilog `ifdef and `endif constructs determine whether or not a macro is defined. These constructs are used to define conditional compilation. If the macro called out by the `ifdef command has been defined, that code is compiled. If not, the code following the `else command is compiled. The `else is not required, but `endif must complete the conditional statement.

The `ifdef and `endif constructs are shown in the following coding example:

`ifdef MYVAR

module if_MYVAR_is_declared;

...

endmodule

10.1

`else

module if_MYVAR_is_not_declared;

...

endmodule `endif

The “Verilog Macros (-define)” command line option allows you to define (or redefine) Verilog macros. This allows you to easily modify the design configuration without any Hardware Description Language (HDL) source modifications, such as for IP core generation and testing flows.

Behavioral Verilog Include Files

Verilog allows separating source code into more than one file. To use the code contained in another file, the current file uses the following syntax:

`include "path/file-to-be-included"

The path can be relative or absolute.

Multiple `include statements are allowed in a single Verilog file. This feature makes your code modular and more manageable in a team design environment where different files describe different modules of the design.

To enable the file in your `include statement to be recognized, identify the directory where it resides, either to ISE™ or to XST.

•Since ISE searches the ISE project directory by default, adding the file to your project directory identifies the file to ISE.

•To direct ISE to a different directory, include a path (relative or absolute) in the `include statement in your source code.

•To point XST directly to your include file directory, use “Verilog Include Directories (–vlgincdir)”

•If the include file is required for ISE to construct the design hierarchy, this file must either reside in the project directory, or be referenced by a relative or absolute path. The file need not be added to the project.

Be aware that conflicts can occur. For example, at the top of a Verilog file you might see the following:

`timescale 1 ns/1 ps `include "modules.v"

...

If the specified file (modules.v) has been added to an ISE project directory and is specified with `include, conflicts may occur. In that case, XST issues an error message:

ERROR:Xst:1068 - fifo.v, line 2. Duplicate declarations of module'RAMB4_S8_S8'