end

Behavioral Verilog Assignment Extension Past 32 Bits

If the expression on the left-hand side of an assignment is wider than the expression on the right-hand side, the left-hand side is padded to the left according to the following rules:

•If the right-hand expression is signed, the left-hand expression is padded with the sign bit:

♦0 for positive

♦1 for negative

♦z for high impedance

♦x for unknown

•If the right-hand expression is unsigned, the left-hand expression is padded with 0s (zeroes).

•For unsized x or z constants only, the following rule applies. If the value of the righthand expression’s left-most bit is z (high impedance) or x (unknown), regardless of whether the right-hand expression is signed or unsigned, the left-hand expression is padded with that value (z or x, respectively).

The above rules follow the Verilog-2001 standard. They are not backward compatible with Verilog-1995.

Behavioral Verilog Tasks and Functions

The declaration of a function or task is intended for handling blocks used multiple times in a design. They must be declared and used in a module. The heading part contains the parameters: input parameters (only) for functions and input/output/inout parameters for tasks. The return value of a function can be declared either signed or unsigned. The content is similar to the combinatorial always block content.

The “Behavioral Verilog Function Declared Within a Module Coding Example” shows a function declared within a module. The ADD function declared is a single-bit adder. This function is called four times with the proper parameters in the architecture to create a 4-bit adder.

The “Behavioral Verilog Function Declared Within a Module Coding Example,” described with a task, is shown in the “Behavioral Verilog Task Declaration and Task Enable Coding Example.”

Behavioral Verilog Function Declared Within a Module Coding Example

module comb15 (A, B, CIN, S, COUT); input [3:0] A, B;

input CIN; output [3:0] S; output COUT;

wire [1:0] S0, S1, S2, S3; function signed [1:0] ADD;

input A, B, CIN; reg S, COUT; begin

S = A ^ B ^ CIN;

COUT = (A&B) | (A&CIN) | (B&CIN); ADD = {COUT, S};

end endfunction

assign S0 = ADD (A[0], B[0], CIN), S1 = ADD (A[1], B[1], S0[1]),

S2 = ADD (A[2], B[2], S1[1]),

S3 = ADD (A[3], B[3], S2[1]),

S = {S3[0], S2[0], S1[0], S0[0]},

COUT = S3[1]; endmodule

Behavioral Verilog Task Declaration and Task Enable Coding Example

The following coding example shows the “Behavioral Verilog Function Declared Within a Module Coding Example” described with a task:

module EXAMPLE (A, B, CIN, S, COUT); input [3:0] A, B;

input CIN; output [3:0] S; output COUT; reg [3:0] S; reg COUT;

reg [1:0] S0, S1, S2, S3;

task ADD;

input A, B, CIN; output [1:0] C; reg [1:0] C; reg S, COUT;

begin

S = A ^ B ^ CIN;

COUT = (A&B) | (A&CIN) | (B&CIN); C = {COUT, S};

end endtask

always @(A or B or CIN) begin

ADD (A[0], B[0], CIN, S0); ADD (A[1], B[1], S0[1], S1); ADD (A[2], B[2], S1[1], S2); ADD (A[3], B[3], S2[1], S3);

S = {S3[0], S2[0], S1[0], S0[0]}; COUT = S3[1];

end endmodule

Behavioral Verilog Recursive Tasks and Functions

Verilog-2001 adds support for recursive tasks and functions. You can use recursion only with the automatic keyword.

Behavioral Verilog Syntax Using Recursion Coding Example

function automatic [31:0] fac; input [15:0] n;

10.1

if (n == 1) fac = 1;

else

fac = n * fac(n-1); //recursive function call endfunction

Behavioral Verilog Constant Functions

Verilog-2001 adds support for constant functions. XST now supports function calls to calculate constant values.

Evaluation of a Constant Function Behavioral Verilog Coding Example

module rams_cf (clk, we, a, di, do); parameter DEPTH=1024;

input clk; input we; input [4:0] a; input [3:0] di;

output [3:0] do;

reg [3:0] ram [size(DEPTH):0];

always @(posedge clk) begin if (we)

ram[a] <= di; end

assign do = ram[a];

function integer size; input depth;

integer i; begin

size=1;

for (i=0; 2**i<depth; i=i+1) size=i+1;

end endfunction

endmodule

Behavioral Verilog Blocking Versus Non-Blocking Procedural Assignments

The pound (#) and asterisk (@) time control statements delay execution of the statement following them until the specified event is evaluated as true. Blocking and non-blocking procedural assignments have time control built into their respective assignment statement. The pound (#) delay is ignored for synthesis.

Behavioral Verilog Blocking Procedural Assignment Syntax Example

The syntax for a blocking procedural assignment is shown in the following coding example:

reg a;

a = #10 (b | c);

or

if (in1) out = 1'b0; else out = in2;