Verilog Attributes and Meta Comments

Verilog Integer Handling

This section discusses Integer Handling, and includes:

•“About Integer Verilog Handling”

•“Integer Handling in Verilog Case Statements”

•“Integer Handling in Verilog Concatenations”

About Integer Verilog Handling

XST handles integers differently from other synthesis tools in several instances. They must be coded in a particular way.

Integer Handling in Verilog Case Statements

Unsized integers in case item expressions may cause unpredictable results. In the following coding example, the case item expression 4 is an unsized integer that causes unpredictable results. To avoid problems, size the 4 to 3 bits as follows:

Integer Handling in Verilog Concatenations

Unsized integers in concatenations may cause unpredictable results. If you use an expression that results in an unsized integer, assign the expression to a temporary signal, and use the temporary signal in the concatenation as follows:

reg [31:0] temp;

assign temp = 4'b1111 % 2; assign dout = {12/3,temp,din};

Verilog Attributes and Meta Comments

This section discusses Verilog Attributes and Meta Comments, and includes:

•“About Verilog Attributes and Meta Comments”

•“Verilog-2001 Attributes”

•“Verilog Meta Comments”

About Verilog Attributes and Meta Comments

XST supports both Verilog-2001 style attributes and meta comments in Verilog. Xilinx recommends Verilog-2001 attributes since they are more generally accepted. Meta comments are comments that are understood by the Verilog parser.

10.1

Verilog-2001 Attributes

Verilog-2001 attributes are bounded by the asterisk character (*). Use the following syntax:

(* attribute_name = "attribute_value" *)

where

•The attribute precedes the signal, module, or instance declaration it refers to.

•The attribute_value is a string. No integer or scalar values are allowed.

•The attribute_value is between quotes.

•The default is 1. (* attribute_name *) is the same as

(* attribute_name = "1" *)

Verilog-2001 Attributes Coding Examples

(* RLOC = "R11C1.S0" *) (* HUSET = "MY_SET" *)

(* fsm_extract = "yes" *) (* fsm_encoding = "gray" *)

Verilog Meta Comments

This section discusses Verilog Meta Comments, and includes:

•“Using Verilog Meta Comments”

•“Writing Verilog Meta Comments”

•“Verilog Meta Comments Coding Examples”

Using Verilog Meta Comments

Use Verilog meta comments to:

•Set constraints on individual objects such as:

♦module

♦instance

♦net

•Set directives on synthesis:

♦parallel_case and full_case directives

♦translate_on translate_off directives

♦all tool specific directives (for example, syn_sharing)

For more information, see “XST Design Constraints.”

Writing Verilog Meta Comments

Meta comments can be written using the C-style (/* ... */) or the Verilog style (// ...) for comments. C-style comments can be multiple line. Verilog style comments end at the end of the line.