EOC Convert

Offset binary output

Clock

FIGURE 10.16

Block diagram of a bipolar-input dual-slope integrating ADC. The output is in offset binary code.

The number of clock cycles required to integrate V2 (2N Tc) to zero is M:

Note that when [Vx] = −VR, M = 0, when [Vx] = 0, M = 2N−1 (1 MSB), and when [Vx] = +VR, M = 2N, giving a true offset binary output code. Note that this dual-slope integrating ADC also has accuracy independent of RC and Tc.

10.5.5Flash Converters

The fastest ADCs are flash converters (FADCs) that enable signal sampling in the ns range and thus are widely used in medical ultrasound systems,

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sonar and radar data conversion, and certain communications applications. Data conversion rates into the hundreds of MSa/sec are typical. Figure 10.17 illustrates an N = 3-bit flash ADC with straight binary output. 2N − 1 = 7 voltage comparators are used for conversion; comparator C1 is used to signal over-range. Thus, an 8-bit FADC uses 255 analog comparators, plus one for over-range. Figure 10.18 illustrates the transfer characteristic of the 3-bit FADC. The Analog Devices AD770 8-bit FADC uses three blocks of 64 comparators and one block of 65 comparators and two levels of bit decoding to

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O.R. = HI

FIGURE 10.18

Transfer characteristic of an ideal 3-bit flash ADC.

obtain an 8-bit ECL-compatible, binary output with a guaranteed 200 MSa/sec rate.

One of the problems in realizing an 8-bit FADC is keeping the dc offset voltages of the 256 comparators small, with low, equal tempcos, and also keeping the resistors matched in the 2N-resistor voltage divider. To realize flash conversions with resolutions greater than 8 bits, a two-step architecture can be used, as shown in Figure 10.19. For example, a 12-bit FADC can be made by letting K = M = 6 bits; thus, each subconverter needs only 26 = 64 comparators. Assuming unipolar operation, 0 ≤ vx ≤ VFS. The output of the K-MSB DAC following a conversion of [vx(nT)] is:

i =1

The input to the M-lesser bits T and H and FADC is:

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M + K = N-bit output

FIGURE 10.19

Architecture of a two-step flash ADC. This design is more efficient when N ≥ 8 is desired.

The voltage difference in parentheses is Ve. Thus, the second FADC generates a binary code on the quantized remnant, Ve, to give a net N = (K + M)-bit output. Because the K- and M-bit FADCs use (2K − 1) and (2M − 1) comparators respectively, the system is generally less expensive and easier to build than a single N-bit FADC. The total coded output of the system is:

When flash converters that sample at over 100 MSa/sec are used, special attention must be paid to how the digital data are handled. High-speed logic (e.g., ECL) must be used and data must be stored temporarily in shift registers and high-speed RAM before permanent recording can take place on a magnetic hard disk or optical disk. FADCs also are greedy for die size and operating power. For every bit increase in FADC resolution, the size of the ADC core circuitry (comparators, resistors, decoding logic) essentially doubles, as does the chip’s power dissipation (Maxim, 2001). Conversion time, however, is independent of the bit resolution, N, and is fast; the state of the art for 2- and 4-bit FADCs is a sample rate of about 1 GSa/sec.

© 2004 by CRC Press LLC

10.5.6Delta–Sigma ADCs

Delta–sigma ADCs are also called oversampled or noise-shaping converters. Oversampling ADCs are based on the principle of being able to trade off accuracy in time for accuracy in amplitude. Figure 10.20 illustrates the circuit of a first -order – ADC. The circuit in the box is a first-order – modulator. The digital filter and decimator produces the N-bit, digital output.

First, the operation of the – modulator in the time domain will be analyzed. Set Vx 0 and let the MOS switch apply −VR to the integrator so that its output, V1, goes positive. The comparator output, V2, applied to the D input of the D flip-flop (DFF) will be HI. At the rising edge of the next clock pulse, HI is seen at the Q output of the DFF. This HI causes the MOS switch to switch the integrator input to +VR, so the integrator output V1 begins to ramp down. When V1 goes negative, the comparator output V2 goes LO. Again when the clock pulse goes HI, the LO at D is sent to the DFF Q output. This LO again sets the MOS switch to −VR, causing V2 to ramp

positively until it goes positive, setting V2 HI, etc.

Figure 10.21 shows the – modulator’s waveforms for Vx = 0. Q is the DFF output, which is the comparator output, V2, latched in when the CP goes high. The peak-to-peak height of the steady-state triangle wave oscillation seen at V1 can easily be shown to be equal to:

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FIGURE 10.21

Waveforms in a first-order – modulator when Vx = 0.

where Tc is the DSDAC’s clock period and the other parameters are given in the figure. The average value of Vs = 0.

Now set Vx = +VR/4 and examine the – ADC’s waveforms (refer to Figure 10.22). Let the system start with V1 = 0 at t = 0 and begin to integrate Vx and Vs = +VR. Initially, the integrator output V1 ramps negative as v1(t) = −[5VR/(4RC)] t. At the first positive-going clock wave, the LO comparator output, V2, is latched to the DFF’s Q output, setting it low. When Q goes low, the MOS switch makes Vs = −VR. Now the integrator output ramps upward with slope +3VR/(4RC). When V1 goes positive, the second positive clock transition latches the HI V2 to Q, setting Vs to +VR. Now the integrator output, V1, ramps down again with slope −5VR/(4RC).

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FIGURE 10.22

Waveforms in a first-order – modulator when Vx = +VR /4.

When V1 < 0, V2 goes LO. The third positive clock transition latches this LO to the Q output of the DFF. As before, this sets Vs to −VR, the integrator output again ramps positive, and the cycle repeats, etc. Note that there is a steady-state (SS) oscillation in V1, V2, Q, and Vs with a period of eight clock periods. The SS duty cycle of Q is 37.5%, and Vs = −¼.

It is also of interest to examine the – ADC’s waveforms when Vx = +VR/2. Now let the system start with V1 = 0 at t = 0 and begin to integrate Vx with Vs = +VR. Assuming Vx is constant, V1 ramps negative as v1(t) = −3VR t/(2RC), causing the comparator output, V2, to be LO. At the first positivegoing clock pulse, the DFF latches the low D input to Q, causing the MOS switch to make Vs = −VR. Now the net input to the integrator is

–VR/2 and the integrator output begins to go positive with slope +VR/(2RC), as shown in Figure 10.23. When V1 first goes positive, V2 goes HI. At the third clock HI transition, the DFF output goes HI, setting the MOS switch to −VR. Now the net input to the integrator is +3VR/2, V1 begins to ramp down again with slope −3VR/(2RC), and the ADC process repeats itself indefinitely until Vx changes. From the waveforms in this figure

where Vx = VR/2, it can be seen that the duty cycle of Q is 25% and Vs =

–½. From the three sets of Vs waveforms, it can be seen that, in general,

Vx = −VR Vs .

Now consider the operation of first-order – ADC. If the number of ones in the output data stream (i.e., the DFF’s Q output) is counted over a sufficient number of samples (clock cycles), the counter’s digital output

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FIGURE 10.23

Waveforms in a first-order – modulator when Vx = +VR /2.

will represent the digital value of the analog input, Vx. Obviously, this method of averaging will only work for DC or low-frequency Vx. In addition, at least 2N clock cycles must be counted in order to obtain N-bit effective resolution. In the – ADC, the modulator’s DFF Q output is the input to the block labeled “digital filter and decimator.” The digital low-pass filter precedes the decimator and serves two functions: (1) it acts as an anti-aliasing filter for the final sampling rate, fo, and (2) it filters out the higher frequency noise produced by the – modulator.

According to Analog Devices’ AN-283 (Sigma–Delta ADCs and DACs):

The final data rate reduction is performed by digitally resampling the filtered output using a process called decimation. The decimation of a discrete-time signal is shown in Figure …, where the sampling rate of the input signal x(n) is at a rate which is to be reduced by a factor of 4. The signal is resampled at the lower rate (the decimation rate), s(n) [ fo]. Decimation can also be viewed as the method by which the redundant signal information introduced by the oversampling process is removed.

In sigma–delta ADCs it is quite common to combine the decimation function with the digital filtering function. This results in an increase in computational efficiency if done correctly.

Figure 10.24 illustrates a heuristic frequency-domain block diagram approximation for a first-order – ADC. To appreciate what happens in the system in the frequency domain, find the transfer function for the analog

© 2004 by CRC Press LLC