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The Differential Amplifier

147

3.4CM and DM Gain of Simple DA Stages at High Frequencies

3.4.1Introduction

Figure 3.7(B) and Figure 3.7(C) illustrate the small-signal, high-frequency models for a JFET DA. Note that the small-signal, high-frequency model (SSHFM) for all FETs includes three small fixed capacitors: the drain-to-source capacitance, Cds; the gate-to-drain capacitance, Cgd; and the gate-to-source capacitance, Cgs. These capacitors, in particular Cgd, limit the high-frequency performance of the JFET DA. The small-signal, drain-source conductance, gd, is also quiescent operating point dependent; it is determined by the upward slope of the FET’s iD vs. vD curves as a function of vGS (see Northrop, 1990, Section 1.6). The transconductance, gm, of the small-signal, voltagecontrolled current source is also Q-point dependent, as shown in Chapter 2.

Figure 3.5 illustrates a simple BJT DA. The hybrid-pi HFSSMs for CM and DM inputs are illustrated in Figure 3.6 after application of the bisection theorem. In the CM and DM HFSSMs, two lumped-parameter, small capacitors can be seen. Cμ is the collector-to-base capacitance, which is on the order of a single pF, and is largely due to the depletion capacitance of the reversebiased pn junction between collector and base; its value is a function of the collector-to-base voltage. However, given a fixed quiescent operating point (Q-point) for the amplifier and small-signal, linear operation, it is possible to approximate Cμ with a fixed value for pencil-and-paper calculations. Cπ models the somewhat larger capacitance of the forward-biased, base–emitter pn junction. It, too, depends on vBE and is generally approximated by its

value at VBEQ. Cμ is generally on the order of 10 to 100 pF; it is larger in power transistors that have larger BE junction areas.

Cs and Ce shunting the common source or emitter resistance to ground, respectively, is on the order of a single pF, but Rs and Re are generally the product of very dynamic current sources (with Norton resistances on the order of tens of megohms), so these capacitances can be very important in determining the high-frequency behavior of the CM gain.

3.4.2High-Frequency Behavior of AC and AD for the JFET DA

It is necessary first to find an algebraic expression for the DM gain of the FET DA at high frequencies. This calculation requires the solution of two simultaneous linear algebraic node equations (Figure 3.7(B)). The node voltages are vg and vod. All the currents are summed, leaving these nodes as positive. After rearranging terms,

vg [s(Cgd + Cgs )+ G1]− vod sCgd = v1d G1

(3.17A)

© 2004 by CRC Press LLC

148

R1

V1

R1

vg

V1

Analysis and Application of Analog Electronic Circuits

 

A

Rd

 

 

 

Rd

 

 

 

vo

 

 

 

 

 

 

Cgd

 

gd

 

gd

Cgd

R1

 

Cds

 

 

 

 

 

 

 

 

vg

 

 

 

 

 

vg

Cgs

gmvgs

vs

 

gmvgs

Cgs

 

 

 

 

 

 

Cs /2

Cs /2

 

 

V1

 

 

2Rs

2Rs

 

 

 

 

 

 

 

 

B

Rd

C

 

 

Rd

 

 

 

 

vod

 

 

vo

 

 

 

Cgd

 

R1

Cgd

 

 

 

 

Cds

gd

Cds

 

gd

 

 

vg

 

 

 

Cgs

gmvgs

Cgs

gmvgs

vs

 

 

 

 

V1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2Rs

Cs

/2

 

 

 

 

 

 

FIGURE 3.5

(A)HFSSM for the complete JFET DA. Note the axis of symmetry splits Rs and Cs symmetrically.

(B)HFSSM of the left half of the DA given DM excitation. (C) HFSSM of the left half of the DA given CM excitation.

vg

[

sCgd

gm

]

+ vod

[

]

 

 

 

(gd

+ Gd )+ s(Cds + Cgd ) = 0

(3.17B)

These two node equations are solved using Cramer’s rule to find the CM gain:

A (s) =

vod

 

 

 

 

[gmrd Rd

(rd + Rd )](1 − sCgd

gm )

 

 

 

 

(3.18)

=

 

 

 

 

 

 

 

 

 

[

gd (

 

 

ds )

 

 

 

]

 

 

 

d )

[

 

 

gs )

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v1d s2 C

C

+ C

+ C

 

C

R r R

r

+ R

+ s C

+ C

R

+

 

 

ds

 

 

 

 

 

gs

 

 

 

gs

1 d

d ( d

 

(

gd

 

1

 

(Cds + Cgd )rd Rd(rd + Rd ) + Cgd gmrd Rd R1(rd + Rd ) + 1]

© 2004 by CRC Press LLC

The Differential Amplifier

149

+Vcc

Rb

Rc

Rc

Rb

 

 

Vo

 

R1

 

 

R1

Vb

 

V

b

V1

V

Ve

 

 

1

 

Re

Re

 

 

 

Re

 

Vcc

FIGURE 3.6

A BJT DA. Note symmetry. The resistors Reare used to raise the DM input resistance.

AD(s) is seen to have a quadratic denominator and a curious high-fre- quency, right-half s-plane zero at gm/Cgd r/s. Its low frequency gain is the same as found in Section 3.2, i.e., −gm rd Rd/(rd + Rd). To find the poles, it is expedient to insert typical numerical parameter values for a JFET DA (Northrop, 1990). Let Cgd = 3 pF; Cgs = 3 pF; Cds = 0.2 pF; Cs = 3 pF; gm = 0.005 S; rd = 105 ohms; Rd = 5 103 ohms; Re = 106 ohms (active current source); and R1 = 103 ohms. After numerical calculations, the zero is found to be at 265 MHz and the two real poles are at 1.687 and 309 MHz. The dc DM gain is 23.8, or 27.5 dB. Thus 20 log AD( f ) is down by 3 dB at 1.687 MHz.

To find AC(s) for the JFET DA, the HFSSM of Figure 3.7(C) is used. Unfortunately, according to the bisection theorem, the voltage, vs, on the axis of symmetry is non-zero, so a third (vs) node must have a node equation written when finding voc. The three node equations are:

 

 

 

vg

[

 

+ s(Cgd

]

[

s Cgd

]

− vs

[

s Cgs

]

= v1c

G1

 

 

 

 

 

G1

+ Cgs ) − voc

 

 

 

 

(3.18A)

−vg

[

s Cgd

− gm

]

 

[

 

 

 

 

]

− vs

[gm + gd + s Cds ]= 0

 

 

 

+ voc (gd

+ Gd )+ s(Cds + Cgd )

(3.18B)

vg [gm + sCgs ]voc [gd + sCds ]+

(3.18C)

vs [s(Cs 2 + Cds + Cgs )+ Gs 2 + gd + gm ]= 0

© 2004 by CRC Press LLC

150

Analysis and Application of Analog Electronic Circuits

A

Rc

vo

 

Rs vb rx

B’ vb

Cµ

C

 

 

B

 

 

 

 

vsc

Rb

Cπ

 

 

go

rπ

 

 

 

 

 

 

 

 

 

gmvb

E

ve

 

 

 

 

 

 

 

 

 

 

Ce/2

 

 

 

 

 

2Re

B

Rc

vo

 

Rs vb rx

B’ vb

Cµ

C

 

 

B

 

 

 

 

vsd

Rb

Cπ

 

 

go

rπ

 

 

 

 

 

 

 

 

 

gmvb

E

ve

 

 

 

 

 

FIGURE 3.7

(A) High-frequency SSM for the left-half BJT DA given common-mode excitation. (B) Highfrequency SSM for the left-half BJT DA given difference-mode excitation.

No one in his right mind would attempt an algebraic solution of a thirdorder system as described by Equation 3.18A through Equation 3.18C on

paper. Clearly, a computer (numerical) simulation is indicated; a circuit analysis program such as pSPICE or MicroCap‘ can be used. Figure 3.8 and

Figure 3.9 show Bode plots of the DM and CM HFSSM frequency responses calculated by the venerable MicroCap‘ III circuit analysis software (which runs under DOS, not Windows‘). Note that the CM frequency response

gain is approximately –46 dB at low frequencies. A zero at approximately 120 kHz causes the CM AR to rise at +20 dB/decade until a pole at approximately 10 MHz causes it to level off. A second pole at approximately 300 MHz causes the CM frequency response to fall off again.

© 2004 by CRC Press LLC

The Differential Amplifier

 

 

151

GAIN

 

DAFETDM

 

PHASE

DB

Temperature = 27

 

Case = 1

DEG

30.00

 

−180.0

 

 

 

18.00 −216.0

6.00 −252.0

−6.00 −288.0

−18.00 −324.0

−30.00

10K

100K

1M

10M

100M

−360.0

1K

1G

Frequency in Hz

FIGURE 3.8

Difference-mode frequency response of the JFET DA of Figure 3.7A. The 3-dB frequency is approximately 1.9 MHz. See text for details.

GAIN

 

 

DAFETCM

 

 

PHASE

DB

Temperature = 27

 

 

Case = 1

 

DEG

0.00

 

 

 

 

 

–180.0

–12.00

 

 

 

 

 

–234.0

–24.00

 

 

 

 

 

–288.0

–36.00

 

 

 

 

 

–342.0

–48.00

 

 

 

 

 

–396.0

–60.00

10K

100K

1M

10M

100M

–450.0

1K

1G

Frequency in Hz

FIGURE 3.9

Common-mode frequency response of the JFET DA of Figure 3.7A. Note that the AR rises +3 dB from 46 dB at 110 kHz, then rises to a maximum of 7 dB and falls off again by 3 dB at approximately 400 MHz. Phase is bold trace with squares.

On the other hand, the DM frequency response is flat at +27.5 dB from dc out to the first real pole at approximately 1.7 MHz. The DM AR then rolls off at –20 dB/decade until the second pole, estimated to be at 310 MHz. However, the zero at 265 MHz pretty much cancels out the effect of the 310-MHz pole on the DM AR.

Note that the decibel CMRR for this amplifier is simply 20 log AD( f ) 20 log AC( f ) . At low frequencies, the CMRR is 27.5 (46) = 73.5 dB and stays this high up to approximately 100 kHz, when it begins to drop off due to the rise in AC( f ) . At 10 MHz, the CMRR has fallen to 21 dB, etc.

© 2004 by CRC Press LLC

152

Analysis and Application of Analog Electronic Circuits

3.4.3High-Frequency Behavior of AD and AC for the BJT DA

Next, examine the high-frequency gain of the simple BJT DA shown in Figure 3.5 for DM and CM inputs. The hybrid-pi HFSSM for BJTs is used. Application of the bisection theorem results in the reduced CM and DM HFSSMs shown in Figure 3.6(A) and Figure 3.6(B). First, the DM HF gain will be found; the DM circuit of Figure 3.6(B) has three nodes: vb, vb′, and vod. The vb node can be eliminated when it is noted that Rb (rx, Rs), so Rb can be set to •, and a new Thevenin resistance, Rs′ = Rs + rx, is defined. Now vb′ and vod must be solved for. Note that ve = 0. The two node equations are written:

v ′ [G ′ + g

π

+ s (C

π

+ C

)] + v

od

[s C

] = v

G

(3.19A)

b s

 

μ

 

μ

sd

s

 

vb′ [gm s Cμ] + vod [go + Gc + s Cμ] = 0

 

(3.19B)

Even though the admittance matrix,

, is second order, its paper-and-pencil

solution is tedious, so MicroCap will be used to solve for the linear DM

HFSSM’s frequency response. In this example, the parameter values are taken to be: Rc = 6.8 kΩ; ro = •; gm = 0.05 S; rπ = 3 kΩ; Re = 106 Ω; Ce = 5 pF; Cμ = 2 pF; Cπ = 30 pF; rx = 10 Ω; and Rs = 50 Ω, Thus Rs′ = 60 Ω. Figure 3.9

shows the DM frequency response Bode plot. The low and mid-frequency gain is 50.4 dB, the −3-dB frequency is approximately 2.0 MHz, and the 0-dB frequency is approximately 410 MHz; this is a frequency well beyond the upper frequency where the hybrid-pi HFSSM is valid.

For CM excitation of the BJT DA, use the linear HFSSM schematic (Figure 3.6(A)). Note that three node equations are required because ve π 0. Again, a computer solution is used for the CM frequency response, shown in Figure. 3.10. Figure 3.10(A) depicts the CM decibel gain and phase for the unrealistic condition of zero parasitic capacitance (Ce) from the BJT emitter to ground. Note that the CM gain is approximately –49 dB at frequencies below 10 kHz,

rises to a peak of –1.3 dB at approximately 30 MHz, and then falls off again at frequencies above 40 MHz. Thus the DA’s CMRR starts at 50.4 – (−49) =

99.4 dB at low frequencies and falls off rapidly above 20 kHz.

Curiously, if Ce = 4 pF is assumed, a radical change in the CM frequency response is seen. Figure 3.10(B) shows the low frequency CM gain to be approximately –49.5 dB; the frequency at which the CM gain is up 3 dB is approximately 14 MHz. It reaches a peak at approximately 200 MHz of –33.8 dB, giving a significant improvement in the BJT DA’s CMRR at high frequencies. Now if Ce is “detuned” by only ±0.2 pF, Figure. 3.10C and Figure 3.10D show that the +3-dB frequency has dropped to approximately 750 kHz and the peak CM gain has risen to –27.2 dB at approximately 320 MHz. It is amazing that the DM gain frequency response is extremely sensitive to Ce, a parasitic parameter over which little control can be exercised; this can be shown when simulating transistor DAs with real transistor models instead of linear HFSSMs. Note that subtle changes in Ce can radically improve or ruin the high-frequency CMRR of a transistor DA.

© 2004 by CRC Press LLC