10.3 Digital-to-Analog Converters (DACs)

10.3.1Introduction

A digital-to-analog converter accepts as inputs an N-bit digital word (0s and 1s) representing a numerical value of an analog output signal and a convert enable (CE) command. A DAC’s output is a voltage or current determined by the digital word input. The output is held until the next word is presented (as parallel or serial data) and the next CE command is given. DACs (voltage or current output) are used in many applications that include but are not limited to: high-fidelity sound systems; analog CRT display systems used in computers and TV; generation of analog signals used in test and measurement systems, etc.

10.3.2DAC Designs

DACs can be classified by whether they use bipolar junction transistor switches or MOS transistor technology. The following DAC architectures are found with MOS technology:

•Binary-weighted resistor DAC

•R–2R ladder

•Inverted R–2R ladder

•Inherent monolithic ladder

•Switched-capacitor DAC

The following DAC designs use BJT technology:

•Binary-weighted current sources

•R–2R ladder using current sources

Figure 10.4 illustrates four common DAC architectures. Figure 10.4(A) shows the binary weighted resistor DAC. This is an impractical design for IC fabrication; one needs accurate resistor ratios over a wide range of resistor values. Also, the op amp is presented with varying input impedances, depending on the input word, thus making the DAC subject to op amp DC bias current errors. The SPDT switches used in this design are generally MOS transistors designed to have very low ON resistance and high OFF resistance. The output voltage of this DAC is given by:

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FIGURE 10.4

Four kinds of DAC circuits using op amps: (A) a binary-weighted resistor DAC (not practical for N > 8); (B) the R–2R ladder DAC; (C) the inverted R–2R ladder DAC; and (D) a binaryweighted current source DAC (not practical for N > 8).

where N is the bit length of the binary “word” being converted and bk is “0” or “1,” depending on the word.

Figure 10.4(B) illustrates the popular R–2R ladder DAC. Here only two resistor values are used; their exact values are not critical, but the ratio must

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be exactly 2 between all 2R and R valued resistors. Switches with low ON resistance and zero offset voltage are required. The output can be shown to be:

Full-scale output voltage occurs when all the switches are set to VR. This is:

The inverted R–2R DAC architecture is shown in Figure 10.4(C). This is a relatively switching glitch-free DAC, well suited for CMOS switches. Note that the ladder resistors’ currents are constant and independent of the switch positions because the op amp’s summing junction is at virtual ground. Bit b1 is the most significant bit (MSB). With b1 = 1 and all others = 0, Vo = −VR/2.

Figure 10.4(D) illustrates the overall architecture of the binary-weighted current source DAC. This circuit is easily implemented with BJT current sources and switches. There are a number of approaches to realizing the switches and current sources for this type of DAC (Franco, 1988). The output voltage of this DAC is given by:

k =1

When the MSB is HI (b1 = 1) and all other bk = 0, Vo = Io R/2; when the LSB is HI (bN = 1) and all other bk = 0, then Vo = Io R/2N.

Figure 10.5 illustrates a simplified schematic of a low-power DAC using switched weighted capacitors (SWC). The MSB output of the SWC DAC can be found by observing that when b1 1, all other bk = 0, and the charge in C1 is also the charge in CF. Also, the summing junction is assumed to be at virtual ground. Thus:

The LSB output of the SWC DAC is found the same way: by assuming bN 1, all other bk = 0.

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Some practical problems emerge in considering the SWC DAC: (1) C1 must have 2N−1 times the area of CN on the substrate. This limits N practically to 8.

(2) The op amp must have a MOS transistor front end to obtain ultra-low bias current so that Vo will not significantly drift over a sampling period.

In Figure 10.6, a design strategy enables the use of a 1:8 capacitor area ratio, rather than a 1:128 area ratio required for the 8-bit DAC shown in Figure 10.5. The MSB output is found from the capacitive voltage divider made from the input array. The input capacitor is C1 = C. It can be shown that the seriesparallel combination of the rest of the capacitors having bk = 0, so they are grounded is C. Thus, Vo(MSB) is simply VR/2. The LSB output is found the same way by considering the capacitor voltage divider; it can be shown to be Vo(LSB) = VR/256. The complete charge-scaling DAC output is given by:

k =1

Multiplying DACs (MDACs) are a special class of DAC in which the reference signal is made variable and the DAC output is the product of the analog value of vR(t) and the digital scaling input. Thus two-quadrant multiplication can be realized for a straight unipolar binary input:

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If the DAC is set up for bipolar offset binary (BOB) operation, true fourquadrant multiplication occurs. The output of a DAC configured for BOB, such as the AD7845 12-bit MDAC, is given by:

MDACs find application in waveform generation; digitally controlled attenuators; programmable power supplies; programmable gain amplifiers;

© 2004 by CRC Press LLC