N

Digital output

FIGURE 10.12

Block diagram of the popular successive-approximation ADC.

The conversion time of an SAADC is Tc = NT, i.e., about N clock periods. For example, the Texas Instruments TLC1225 12-bit SAADC can convert in 12 μs, given a 2-MHz clock input. The TI TLC1550I 10-bit SAADC can convert in 6 μs, given a 7.8-MHz clock, which is about 166 kSa/sec.

10.5.4Integrating Converters

Integrating converters are also called serial analog DACs. Two basic architectures will be considered in this section: (1) single-slope and (2) dualslope integrating DACs (IDACs). Figure 10.14 illustrates the block diagram of one version of a single-slope IDAC (SSIDAC). An op amp integrator that can be reset is used as a ramp generator; it integrates the DC VR < 0 to produce a positive ramp with slope VR/RC. The ramp, V2, is the negative input to a comparator, the positive input to which is the held signal being converted, [Vx] > 0.

At the start of conversion [Vx] > V2, so the comparator output, Q, is HI, enabling the AND gate to pass clock pulses to the binary counter. When V2 > [Vx], Q goes LO. This event stops the counting and, through the control logic, causes the integrator to be reset to V2 0 and the track and hold circuit to again track vx(t). Q 0 also causes the counter to present the total count at its parallel output and the control logic to signal end of conversion (EOC). The SSIDAC is now in standby mode waiting

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Standby for next start

FIGURE 10.13

Logical flowchart illustrating the steps in one conversion cycle of a successive-approximation ADC.

EOC

Convert

FIGURE 10.14

Block diagram of a single-slope integrating ADC.

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for the next convert (CON) command. The leading edge of the CON command causes the counter to be reset; vx(t) to be held; the integrator to begin integrating VR; and the counter to begin counting. Each completed conversion count, M, is proportional to that [Vx]. From the SSIDAC architecture, the jth conversion:

Suppose a 10-bit converter is desired and Vx ranges from 0 to 10 V. Let VR = 1.00 V and T = 10−6 sec. Then, from the preceding equation, it can be determined that RC = 1.023 ∞ 10−4 sec, so if C = 10−8 F, then R = 1.023 ∞ 104 Ω. With these parameters, the SSIADC will output Mj = 210 – 1 when [Vx]j = 10.0 V. Note that SSIADC conversion time is variable; the larger [Vx]j is, the longer it takes. When [Vx]j = 10 V, conversion takes 1.023 MS. Thus, integrating ADCs (IADCs) are relatively slow, suitable for ECG and DC applications. Also, accuracy of the SSIADC depends on the stability of the RC product and clock period over time and temperature changes. To overcome these problems, the clever design of the dual-slope integrating ADC was developed.

Figure 10.15 illustrates a unipolar dual-slope integrating ADC. Note it does not require a DAC. On receiving the convert command, this ADC first resets its integrator output to V2 = 0 and clears its counter to zero. S1 connects the integrator to Vx > 0. Vx is integrated for 2N clock cycles or 2N Tc sec, causing V2 to go negative. At the end of this integration time, the counter is again cleared and S1 switches to −VR, which is integrated, causing V2 to ramp positively toward zero. During this interval, the counter counts up from zero because Q is high. When V2 reaches zero, the comparator output Q goes from HI to LO, stopping the counter and signaling the end of the conversion cycle. Mathematically, the integrator output when the counter reaches T1 = 2N Tc is:

In the second part of the conversion cycle, the integrator integrates until V2 reaches zero. This takes M clock cycles. Mathematically:

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Clock

FIGURE 10.15

Block diagram of a unipolar-input dual-slope integrating ADC.

VR

Therefore, the countdown time (and thus M) is proportional to the average of the input signal over T1 = 2N Tc sec. Note that this ADC is independent of RC and Tc; these parameters are determined from practical considerations. Often T1 is made 1/60 sec to make the ADC reject 60-Hz hum on vx(t) (Northrop, 1990). Figure 10.16 illustrates the block diagram of a dual-slope integrating ADC (DSIADC).

This ADC gives an offset binary output code for bipolar DC input signals. When the convert command is given, the input is held, the counter is cleared (reset to zero), and V2 is set to zero with S2. Next, S2 is opened and S1 is set to integrate the output of OA-1, V2, for a time equal to 2N clock cycles (T1 = 2N Tc). V2 goes positive, so Q = LO, disabling the output counter. When T1 = 2N Tc, the counter is enabled and counts clock pulses, and S1 is set to integrate +VR. V2 now ramps down to zero, which is sensed by the comparator output Q going HI. The number of clock cycles required for V2 to go to 0 is M. The peak V2 is found by:

© 2004 by CRC Press LLC