14.12 Bibliography

Books by Feugate and McIntyre [ 1988], Cheng and Agrawal [ 1989], and Fritzemeier, Nagle, and Hawkins [ 1989] contain explanations of basic testing terms and techniques. The book by Abramovici, Breuer, and Friedman [ 1990] is an advanced undergraduate and graduate-level review of test techniques. Needham s [ 1991] book reviews wafer and package testing. The text by Russell and Sayers [ 1989] is an undergraduate-level text with explanations of test algorithms. Turino s [ 1990] book covers a wide range of testing topics.

There are a number of books with collections of research papers on test, including works by Eichelberger, Lindblom, Waicukauski, and Williams [ 1991]; Lombardi and Sami [ 1987]; Williams [ 1986]; and Zobrist [ 1993]. Tsui s book contains a review of scan test and a large bibliography [ 1987]. The book by Ghosh, Devadas, and Newton [ 1992] describes test-generation algorithms for state machines at a level intended for CAD researchers. Bardell, McAnney, and Savir [ 1987] focus on pseudorandom BIST. A book by Yarmolik [ 1990] covers BIST and signature analysis; a second book by Yarmolik and Kachan [ 1993] concentrates on self-test. Books by Lavagno and Sangiovanni-Vincentelli [ 1993] and by Lee [ 1997] are advanced works on the integration of test synthesis and logic synthesis. The text by Jha and Kundu [ 1990] covers reliability in design. The book by Bhattacharya and Hayes [ 1990] covers modeling for testing (and includes a good description of the D and PODEM algorithms). There are alternative ASIC test techniques that we have not covered. For example, Chandras paper describes the CrossCheck architecture for gate arrays [ 1993]. A book by Chakradhar, Agrawal, and Bushnell [ 1991] covers neural models for testing.

The major conferences in the area of test are the International Test Conference, known as the ITC (TK7874.I593, ISSN 0743-1686), the International Test Symposium (TK7874.I3274, ISBN depends on year), and the European Design and Test Conference (TK7888.4.E968, 1994: ISBN 0-8186-5410-4). The IEEE International Workshop on Memory Technology, Design, and Testing (TK7895.M4.I334) is a conference on memory testing. US DoD standard procedure 5012 of Mil-Std-883 sets requirements for simulation algorithms, fault collapsing, undetectable faults, potential detection, and detection strobing (see also IEEE Design & Test Magazine, Sept. 1993, pp. 68 79).

The IEEE has published a series of tutorials on test: VLSI Support Technologies: Computer-Aided Design, Testing, and Packaging, TK7874.T886, 1982; VLSI Testing & Validation Techniques, ISBN 0818606681, TK7874.T8855, 1985; Test Generation for VLSI Chips, ISBN 081868786X, TK7874.T8857, 1988.

The Waveform and Vector Exchange Specification ( WAVES ), IEEE Std 1029.1-1991 [ IEEE 1029.1-1991], is a standard representation for digital stimulus and response for both design and test and allows digital stimulus and response information to be exchanged between different simulation and test tools. The syntax of WAVES is a subset of VHDL. WAVES was developed by the WAVES Analysis and Standardization Group ( WASG ). The WASG was jointly sponsored by the Automatic Test Program Generation (ATPG) subcommittee of the Standards Coordination Committee 20 ( SCC20) and the Design Automation Standards Subcommittee ( DASS ) of the Computer Society.

14.13 References

Page numbers in brackets after the reference indicate the location in the chapter body.

Abramovici, M., M. A. Breuer, and A. D. Friedman. 1990. Digital Systems Testing and Testable Design. New York: W. H. Freeman, 653 p. ISBN 0-7167-8179-4. TK7874.A23. Introduction to testing and BIST. See also Breuer, M. A., and A. D. Friedman, 1976. Diagnosis and Reliable Design of Digital Systems. 2nd ed. Potomac, MD: Computer Science Press, ISBN 0-914894-57-9. TK7868.D5B73. [ reference location ]

Agarwal, V. K., and A. S. F. Fung. 1981. Multiple fault testing of large circuits by single fault test sets. IEEE Transactions on Computing, Vol. C-30, no. 11, pp. 855 865. [ reference location ]

Bardell, P. H., W. H. McAnney, and J. Savir. 1987. Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley, 354 p. ISBN 0-471-62463-2. TK7874.B374. [ reference location ]

Bartlett, K., et al. 1988. Multilevel logic minimization using implicit don t cares, IEEE Transactions on Computer-Aided Design, Vol. CAD-7, no. 6, pp. 723 740. [ reference location ]

Bhattacharya, D., and J. P. Hayes. 1990. Hierarchical Modeling for VLSI Circuit Testing. Boston: Kluwer, 159 p. ISBN 079239058X. TK7874.B484. Contains a good description of the D and PODEM algorithms. [ reference location ]

Bleeker, H., P. v. d. Eijnden, and F. de Jong. 1993. Boundary-Scan Test: A Practical Approach. Boston: Kluwer, 225 p. ISBN 0-7923-9296-5. [ reference location ]

Brayton, R. K., G. D. Hachtel, and A. L. Sangiovanni-Vincentelli. 1990.Multilevel logic synthesis. Proceedings of the IEEE, Vol. 78, no. 2, pp. 264 300 [ reference location ]

Butler, K. M., and M. R. Mercer. 1992. Assessing Fault Model and Test Quality. Norwell, MA: Kluwer, 125 p. ISBN 0-7923-9222-1. TK7874.B85. Introductory level discussion of test terminology, fault models and their limitations.

Research-level discussion of the use of BDDs, ATPG, and controllability/observability. [ reference location ]

Chandra, S., et al. 1993. CrossCheck: an innovative testability solution. IEEE Design & Test of Computers, Vol. 10, no. 2, pp. 56 68. Describes a gate-array test architecture used by Sony, for example. [ reference location ]

Chakradhar, S. T., V. D. Agrawal, and M. L. Bushnell. 1991. Neural Models and Algorithms for Digital Testing. Boston: Kluwer, 184 p. ISBN 0792391659. TK7868.L6.C44. [ reference location ]

Cheng, K.-T., and V. D. Agrawal. 1989. Unified Methods for VLSI Simulation and Test Generation. Norwell, MA: Kluwer, 148 p. ISBN 0-7923-9025-3. TK7874.C525. 377 references. The first three chapters give a good introduction to fault simulation and test vector generation. [ reference location ]

Eichelberger, E. B., E. Lindblom, J. A. Waicukauski, and T. W. Williams. 1991. Structured Logic Testing. Englewood Cliffs, NJ: Prentice-Hall, 183 p. ISBN 0-13-8536805. TK7868.L6S78. Includes material printed in 19 articles by the authors from 1987 to 1989. [ reference location ]

Feugate Jr., R. J., and S. M. McIntyre. 1988. Introduction to VLSI Testing. Englewood Cliffs, NJ: Prentice-Hall, 226 p. ISBN 0134988663. TK7874 .F48. Chapters on: Automated Testing Overview; IC Fabrication and Device Specifications; Testing Integrated Circuits: Parametric Tests; Functional Tests; Example of a Functional Test Program; Characterization testing; Developing Test Patterns; Special Testing Problems: Memories; Special Testing Problems: Microcontrollers; Design for Testability; LSTL Language Summary; Example of a Production Test program; The D-Algorithm. [ reference location ]

Fujiwara, H., and T. Shimono. 1983. On the acceleration of test generation algorithms. IEEE Transactions on Computers, Vol. C-32, no. 12, pp. 1137 1144. Describes the FAN ATPG algorithm. [ reference location ]

Fritzemeier, R. R., H. T. Nagle, and C. F. Hawkins. 1989. Fundamentals of testability a tutorial. IEEE Transactions on Industrial Electronics, Vol. 36, no. 2, pp. 117 128. 54 refs. A review of testing, failure mechanisms, fault models, fault simulation, testability analysis, and test-generation methods for CMOS VLSI circuits. [ reference location ]

Ghosh, A., S. Devadas, and A. R. Newton. 1992. Sequential Logic Testing and Verification. Norwell, MA: Kluwer, 214 p. ISBN 0-7923-91888. TK7868.L6G47. Describes test generation algorithms for state machines at a level intended for CAD researchers. [ reference location ]

Goel, P. 1981. An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Transactions on Computers, Vol. C-30, no. 3, pp. 215 222. [ reference location ]

Goldstein, L. H. 1979. Controllability/observability analysis of digital circuits. IEEE Transactions on Circuits and Systems, Vol. CAS-26, no. 9, pp. 685 693.

Describes SCOAP measures. [ reference location ]

Golomb, S. W., et al. 1982. Shift Register Sequences. 2nd ed. Laguna Hills, CA: Aegean Park Press, 247 p. ISBN 0-89412-048-4. QA267.5.S4 G6. See also: Golomb, S. W., Shift Register Sequences (with portions co-authored by L. R. Welch, R. M. Goldstein and A. W. Hales). San Francisco: Holden-Day (1967), 224 p. QA267.5.S4 G6. The second edition has a long bibliography. [ reference location ]

Gulati, R. K., and C. F. Hawkins. (Ed.). 1993. IDDQ Testing of VLSI Circuits. Boston: Kluwer, 120 p. ISBN 0792393155. TK7874.I3223. [ reference location ]

Hughes, J. L. A., and E. J. McCluskey. 1986. Multiple stuck-at fault coverage of single stuck-at fault test sets. In Proceedings of the IEEE International Test Conference, pp. 368 374. [ reference location ]

IEEE 1029.1. 1991. IEEE Standard for Waveform and Vector Exchange (WAVES) (ANSI). 96 p. IEEE reference numbers: [1-55937-195-1] [SH15032-NYF]. [ reference location ]

IEEE 1149.1b. 1994. IEEE Std 1149.1-1990 Access Port and Boundary-Scan Architecture. 176 p. The first part of this updated standard includes supplement 1149.1a-1993. IEEE reference numbers: [1-55937-350-4] [SH16626-NYK] The second part of this standard is includes 1149.1b-1994 Supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture (ANSI) (available separately). 80 p. IEEE reference numbers: [1-55937-497-7] [SH94256-NYK]. [ reference location , reference location , reference location , reference location , reference location , reference location ]

Jha, N. K., and S. Kundu. 1990. Testing and Reliable Design of CMOS Circuits. Boston: Kluwer, 231 p. ISBN 0792390563. TK7871.99.M44.J49. [ reference location ]

Lavagno, L., and A. Sangiovanni-Vincentelli. 1993. Algorithms for Synthesis and Testing of Asynchronous Circuits. Boston: Kluwer, 339 p. ISBN 0792393643. TK7888.4.L38. [ reference location ]

Lee, M. T.-C. 1997. High-Level Test Synthesis of Digital VLSI Circuits. Boston: Artech House, ISBN 0890069077. TK7874.75.L44. [ reference location ]

Lombardi, F., and M. Sami (Ed.). 1987. Testing and Diagnosis of VLSI and ULSI. Norwell, MA: Kluwer, 533 p. ISBN 90-247-3794-X. TK7874.N345. A series of 20 research-level papers presented at a NATO advanced Study Institute. Contents: Trends in Design for Testability; Statistical Testing; Fault Models; Fault Detection and Design for Testability of CMOS Logic Circuits; Parallel Computer Systems Testing and Integration; Analog Fault Diagnosis; Spectral Techniques for Digital Testing; Logic Verification, Testing and Their Relationships to Logic Synthesis; Proving the Next Stage from Simulation; Petri

Nets and Their Relation to Design Validation and Testing; Functional Test of ASICs and Boards; Fault Simulation Techniques Theory and Practical Examples; Threshold-Value Simulation and Test Generation; Behavioral Testing of Programmable Systems; Testing of Processing Arrays; Old and New Approaches for the Repair of Redundant Memories; Reconfiguration of Orthogonal Arrays by Front Deletion; Device Testing and SEM Testing Tools; Advances in Electron Beam Testing. [ reference location ]

Maunder, C. M., and R. E. Tulloss (Ed.). 1990. The Test Access Port and Boundary-Scan Architecture. Washington, DC: IEEE Computer Society Press. ISBN 0-8186-9070-4. TK867.T39. [ reference location ]

Needham, W. M. 1991. Designer's Guide to Testable ASIC Devices. New York: Van Nostrand Reinhold, 284 p. ISBN 0-442-00221-1. TK7874.N385. Practical review of wafer and package testing. Includes summary of features and test file formats used by logic testers. [ reference location ]

Parker, K. P. 1992. The Boundary-Scan Handbook. Norwell, MA: Kluwer, 262 p. ISBN 0-7923-9270-1. TK7868.P7 P3. Describes BSDL. [ reference location ]

Rajsuman, R. 1994. Iddq Testing for CMOS VLSI. Boston: Artech House, 193 p. ISBN 0-89006-726-0. TK7871.99.M44R35. [ reference location ]

Rao, G. K. 1993. Multilevel Interconnect Technology. New York: McGraw-Hill. ISBN 0-07-051224-8. Covers the design of a multilevel interconnect process, and manufacturing and reliability issues. [ reference location ]

Roth, J. P. 1966. Diagnosis of automata failures: A calculus and a method. IBM Journal of Research and Development, Vol. 10, no. 4, pp. 278 291. Describes the D-calculus and the D-algorithm. [ reference location ]

Russell, G., and I. L. Sayers. 1989. Advanced Simulation and Test Methodologies for VLSI Design. London: Van Nostrand Reinhold (International), 378 p. ISBN 0-7476-0001-5. TK7874.R89. Good explanations with a simple example of the D-algorithm. [ reference location ]

Sabnis, A. G. (Ed.). 1990. VLSI Reliability. San Diego: Academic Press. ISBN 0-12-234122-8. Covers ESD, electromigration, packaging issues, quality assurance, failure analysis, radiation damage. [ reference location ]

Scheiber, S.F. 1995. Building a Successful Board-Test Strategy. Boston: Butterworth Heineman, 286 p. ISBN 0-7506-9432-7. TK7868.P7S33. Practical description from a management point of view of board-level testing. [ reference location ]

Schulz, M. H., E. Trischler, and T. M. Sarfert. 1988. SOCRATES: a highly efficient automatic test pattern generation system. IEEE Transactions on Computer-Aided Design, Vol. 7, no. 1, pp. 126 137. [ reference location ]

Turino, J. 1990. Design to Test A Definitive Guide for Electronic Design, Manufacture and Service. 2nd ed. New York: Van Nostrand Reinhold, 368 p. ISBN 0-442-00170-3. TK7874.T83. A small encyclopedia of testing. Includes a general introduction to testability, and guidelines for: system-level, analog, and general circuit testing; board-level guidelines, boundary scan, built-in test, testability buses, mechanical issues, surface-mount technology, test software, documentation, implementation, ad-hoc test techniques and strategies, testability checklists, and a testability rating system. [ reference location ]

Tsui, F. F. 1987. LSI/VLSI Testability Design. New York: McGraw-Hill, 700 p. ISBN 0-07-065341-0. TK7874.T78. Extensive review of scan-test techniques. Approximately 100-page bibliography of papers published on test from 19621986. [ reference location ]

Williams, T. W. (Ed.). 1986. VLSI Testing. Amsterdam: Elsevier Science, 275 p. ISBN 0-444-87895-5 (part of set 0-444-87890-4). TK7874.V5666. Seven papers on fault modeling, test generation, and fault simulation, testable PLA designs, design for testability, memory testing, semiconductor test equipment, and board level test equipment. [ reference location ]

Yarmolik, V. N. 1990. Fault Diagnosis of Digital Circuits. New York: Wiley. Translated from Russian text. Covers D-algorithm, LSSD, random and pseudorandom testing and analysis, and signature analysis. [ reference location ]

Yarmolik, V. N., and I. V. Kachan. 1993. Self-Testing VLSI Design. New York: Elsevier, 345 p. ISBN 0-444-89640-6. TK7874.I16. Extensive reference on pseudorandom testing techniques. Includes description of pseudorandom sequence generators and polynomials. [ reference location ]

Zobrist, G.W. (Ed.). 1993. VLSI Fault Modeling and Testing Techniques. Norwood, NJ: Ablex, 199 p. ISBN 0-89391-781-8. TK7874.V5625. Includes six research-level papers on physical fault modeling, testing of CMOS open faults, testing bridging faults, BIST for PLAs, design for testability, and synthesis methods for testable circuits. [ reference location ]

Last Edited by SP 14112004

ASIC

CONSTRUCTION

A town planner works out the number, types, and sizes of buildings in a development project. An architect designs each building, including the arrangement of the rooms in each building. Then a builder carries out the construction according to the architect s drawings. Electrical wiring is one of the last steps in the construction of each building. The physical design of ASICs is normally divided into system partitioning, floorplanning, placement, and routing. A microelectronic system is the town and the ASICs are the buildings. System partitioning corresponds to town planning, ASIC floorplanning is the architect s job, placement is done by the builder, and the routing is done by the electrician. We shall design most, but not all, ASICs using these design steps.