B.4 Verilog HDL LRM

An important feature of Verilog is the ability to extend tools by writing your own code and integrating it with a Verilog-based tool. For example, the following code calls a user-written system task, $hello :

initial $hello(a_reg);

Here is the C program, hello.c , that prints the full hierarchical name of the instance in which the Verilog code containing the call to $hello is located:

#include "veriuser.h"

#include "acc_user.h"

int hello()

{ handle mod_handle; char *full_name; acc_initialize();

mod_handle = acc_handle_tfarg(1);

io_printf("Hello from: %s\n", acc_fetch_fullname(mod_handle));

acc_close(); }

The details of how to compile and link your program with the Verilog executable depend on the particular tool; the names, functions, and parameters of ACC routines, the header files, veriuser.h and acc_user.h (most companies include these with their Verilog products), as well as older TF routines and the newer VPI routines are described in detail in Sections 17 23 of the 95 LRM.

Annex F of the 95 LRM describes widely used Verilog system tasks and functions that are not required to be supported as part of IEEE Std 1364-1995. Table B.3 summarizes these tasks and functions. Annex G of the 95 LRM describes additional compiler directives that are not part of IEEE Std 1364-1995 and are not often used by ASIC designers. Two directives, `default_decay_time and `default_trireg_strength , are used to model charge decay and the strength of high-impedance trireg nets. Four more compiler directives: `delay_mode_distributed , `delay_mode_path , `delay_mode_unit, and `delay_mode_zero are used to specify the delay mode for modules.

TABLE B.3 System tasks and functions (not required in IEEE Std 1364-1995).

$countdrivers ( net, [ net_is_forced, number_of_01x_drivers, number_of_0_drivers,

number_of_1_drivers, number_of_x_drivers ] ) ;

Returns a 0 if there is no more than one driver on the net and returns a 1 otherwise (indicating contention).

$getpattern ( mem_element ) ; // Drive a pattern from an indexed memory. Example: assign {i1, i2, i3, i4} = $getpattern ( mem [ index ] )

$input ("filename"); // Allows input from file rather than terminal.

$key [ ( "filename" ) ] ; $nokey ; // Enable/disable key file in interactive mode. $list [ ( hierarchical_name ) ] ; // List current or specified object.

$log [ ( "filename" ) ] ; $nolog ; // Enable/disable log file for standard output. $reset [ ( stop_value [ , reset_value , [ diagnostics_value ] ] ) ] ; // Reset time.

$reset_count ; // Count the number of resets.

$reset_value ; // Pass information prior to reset to simulation after reset. $save ( "file_name" ) ; // Save simulation for later restart.

$restart ( "file_name" ) ; // Restart simulation from saved file.

$incsave ( "incremental_file_name" ) ; // Save only changes since last $save $scale ( hierarchical_name ) ; // Convert to time units of invoking module. $scope ( hierarchical_name ) ; // Sets the specified level of hierarchy as current scope.

$showscopes [ ( n ) ]; // Show scope (n = none or zero) else show all items below scope.

$showvars [ ( list_of_variables ) ] ; // Show status of scope or specified variables.

$sreadmemb ( mem_name , start_address , finish_address , string { , string } ) ;

$sreadmemh ( mem_name , start_address , finish_address , string { , string } ) ;

Load data into mem_name from character string (same format as $readmemb/h ).

B.5 Bibliography

There are fewer books available on Verilog than on VHDL. The best reference book is the IEEE Verilog HDL LRM [IEEE 1364-1995]; it is detailed as well as containing many examples. In addition to the references given in Chapter 11, the following books concentrate on Verilog: Sternheim, Singh, and Trivedi [1990] (Yatin Trivedi was the technical editor for the 95 LRM); Thomas and Moorby [1991]; Smith [1996]; and Golze and Blinzer [1996]. Capilano Computing Systems has produced a book to accompany its Verilog Modeler product [Capilano, 1997].

Sandstrom compiled an interesting cross-reference between Verilog and VHDL (a 2.5 page table listing the correspondence between major constructs in both languages) in a pull-out supplement to Integrated System Design Magazine . An electronic version of this article is at http://www.isdmag.com (the article is labeled January 1996, but filed under October 1995). Other online articles related to Verilog at www.isdmag.com , include case studies of Sun Microsystems ULTRASparc-1 (June 1996) and Hewlett Packard s PA-8000 (January, February, and March 1997); both CPUs were designed with Verilog behavioral models. The March 1997 issue also contains an article on the recent history and the future plans of Open Verilog International ( OVI). OVI helped create IEEE Std 1364-1995 and sponsored the annual International Verilog HDL Conference (IVC). In 1997 the IVC merged with the VHDL International Users Forum ( VIUF ) to form the IVC/VIUF Conference (see http://www.hdlcon.org ).

In January of 1995 OVI reactivated the Technical Coordinating Committee ( TCC) to recommend updates and changes to Verilog HDL. The TCC comprises technical subcommittees ( TSC), which are developing a delay calculator standard ( LM-TSC), analog extensions to Verilog HDL ( VA-TSC), an ASIC library modeling standard ( PS-TSC), cycle-based simulation standard ( VC-TSC), timing-constraint formats ( VS-TSC), as well as Verilog language enhancements and extensions ( VD-TSC). Links and information about OVI are available at http://www.avanticorp.com and http://www.chronologic.com . The OVI web site is http://www.verilog.org/ovi . Information on the activities of the OVI committees is available at the Meta-Software site, ftp://ftp.metasw.com/pub

.

The work of the OVI and IEEE groups is related. For example, the IEEE Design Automation Standards Committee ( DASC) contains the Verilog Working Group ( PAR 1364), the Circuit Delay and Power Calculation ( DPC) System Study

Group ( P1481), as well as the VHDL and other WGs. Thus, the OVI DC-TSC directory contains the Standard Delay Calculation System ( DCS) Specification (v1.0) approved by OVI/CFI and currently being studied by the IEEE DPC Study Group. DCS provides a standard system for designers to calculate chip delay and power using the following methods: Delay Calculation Language ( DCL) from IBM and CFI, Detailed Standard Parasitic Format ( DSPF) and Reduced Standard Parasitic Format ( RSPF) from Cadence Design Systems (combined into a new Standard Parasitics Exchange Format, SPEF), and Physical Design Exchange Format ( PDEF) from Synopsys. The current IEEE standardization work is expanding the scope to add power calculation. Thus, useful information relating to Verilog may be found at the VHDL site, VIUF Internet Services ( VIIS at http://www.vhdl.org ), as well as the OVI site.

Two usenet newsgroups are related to Verilog: comp.lang.verilog and comp.cad.synthesis . In January of 1997 the Verilog news archive was lost due to a disk problem. While attempts are made to restore the archive, the Verilog Frequently Asked Questions (FAQ) list is still available at http://www.lib.ox.ac.uk/internet/news/faq/archive/verilog-faq.html . A list of CAD-related newsgroups (including comp.lang.verilog ) is maintained at Sun Microsystems DACafe ( http://www.ibsystems.com/DACafe/TECHNICAL/Resources/NewsGps.html

. Sun ( ~/DACafe/USERSGROUPS ) also maintains the following user groups that often discuss Verilog: Cadence, Mentor Graphics, Synopsys, VeriBest, and Viewlogic. A number of tools and resources are available on the World Wide Web, including Verilog modes for the emacs editor; Verilog preprocessors in Perl and C (which allow the use of `define and `ifdef with logic synthesis tools, for example); and demonstration versions of the following simulators: Viper from InterHDL ( http://www.interhdl.com ) and VeriWell from Wellspring Solutions ( http://www.wellspring.com ). VeriWell now supports the Verilog PLI, including the acc and tf routines in IEEE Std 1364-1995 (requiring Visual C++ 4.0 or newer for the Windows version, Code Warrior 9 or newer for the Macintosh, and GNU C 2.7.0 or newer for the Linux and Sparc versions).

Several personal Web pages focus on Verilog HDL; these change frequently but can be found by searching. Actel has placed a number of Verilog examples (including synthesizable code for a FIFO and a RAM) at its site: http://wwwtest.actel.com/HLD/verimain.html . Many universities maintain Web pages for Verilog-related classes. Examples are the Web site for the ee282 class at Stanford ( http://lummi.Stanford.EDU/class/ee282 ), which contains Verilog models for the DLX processor in the second edition of Hennessy and Patterson sComputer Architecture: A Quantitative Approach ; and course material for 18-360, Introduction to Computer-Aided Digital Design, by Prof. Don Thomas at http://www.ece.cmu.edu .