- •INTRODUCTION TO ASICs
- •1.1 Types of ASICs
- •1.2 Design Flow
- •1.3 Case Study
- •1.4 Economics of ASICs
- •1.5 ASIC Cell Libraries
- •1.6 Summary
- •1.7 Problems
- •1.8 Bibliography
- •1.9 References
- •CMOS LOGIC
- •2.12 References
- •2.1 CMOS Transistors
- •2.2 The CMOS Process
- •2.3 CMOS Design Rules
- •2.4 Combinational Logic Cells
- •2.5 Sequential Logic Cells
- •2.6 Datapath Logic Cells
- •2.7 I/O Cells
- •2.8 Cell Compilers
- •2.9 Summary
- •2.10 Problems
- •2.11 Bibliography
- •ASIC LIBRARY DESIGN
- •3.1 Transistors as Resistors
- •3.3 Logical Effort
- •3.4 Library-Cell Design
- •3.5 Library Architecture
- •3.6 Gate-Array Design
- •3.7 Standard-Cell Design
- •3.8 Datapath-Cell Design
- •3.9 Summary
- •3.10 Problems
- •3.11 Bibliography
- •3.12 References
- •PROGRAMMABLE ASICs
- •4.1 The Antifuse
- •4.2 Static RAM
- •4.4 Practical Issues
- •4.5 Specifications
- •4.6 PREP Benchmarks
- •4.7 FPGA Economics
- •4.8 Summary
- •4.9 Problems
- •4.10 Bibliography
- •4.11 References
- •5.1 Actel ACT
- •5.2 Xilinx LCA
- •5.3 Altera FLEX
- •5.4 Altera MAX
- •5.5 Summary
- •5.6 Problems
- •5.7 Bibliography
- •5.8 References
- •6.1 DC Output
- •6.2 AC Output
- •6.3 DC Input
- •6.4 AC Input
- •6.5 Clock Input
- •6.6 Power Input
- •6.7 Xilinx I/O Block
- •6.8 Other I/O Cells
- •6.9 Summary
- •6.10 Problems
- •6.11 Bibliography
- •6.12 References
- •7.1 Actel ACT
- •7.2 Xilinx LCA
- •7.3 Xilinx EPLD
- •7.4 Altera MAX 5000 and 7000
- •7.5 Altera MAX 9000
- •7.6 Altera FLEX
- •7.7 Summary
- •7.8 Problems
- •7.9 Bibliography
- •7.10 References
- •8.1 Design Systems
- •8.2 Logic Synthesis
- •8.3 The Halfgate ASIC
- •8.3.4 Comparison
- •8.4 Summary
- •8.5 Problems
- •8.6 Bibliography
- •8.7 References
- •9.1 Schematic Entry
- •9.3 PLA Tools
- •9.4 EDIF
- •9.5 CFI Design Representation
- •9.6 Summary
- •9.7 Problems
- •9.8 Bibliography
- •9.9 References
- •VHDL
- •10.1 A Counter
- •10.2 A 4-bit Multiplier
- •10.3 Syntax and Semantics of VHDL
- •10.5 Entities and Architectures
- •10.6 Packages and Libraries
- •10.7 Interface Declarations
- •10.8 Type Declarations
- •10.9 Other Declarations
- •10.10 Sequential Statements
- •10.11 Operators
- •10.12 Arithmetic
- •10.13 Concurrent Statements
- •10.14 Execution
- •10.15 Configurations and Specifications
- •10.16 An Engine Controller
- •10.17 Summary
- •10.18 Problems
- •10.19 Bibliography
- •10.20 References
- •IEEE Language Reference Manual project
- •VERILOG HDL
- •11.1 A Counter
- •11.2 Basics of the Verilog Language
- •11.3 Operators
- •11.4 Hierarchy
- •11.5 Procedures and Assignments
- •11.6 Timing Controls and Delay
- •11.7 Tasks and Functions
- •11.8 Control Statements
- •11.9 Logic-Gate Modeling
- •11.10 Modeling Delay
- •11.11 Altering Parameters
- •11.12 A Viterbi Decoder
- •11.13 Other Verilog Features
- •11.14 Summary
- •11.15 Problems
- •11.16 Bibliography
- •11.17 References
- •12.2 A Comparator/MUX
- •12.3 Inside a Logic Synthesizer
- •12.6 VHDL and Logic Synthesis
- •12.8 Memory Synthesis
- •12.9 The Multiplier
- •12.10 The Engine Controller
- •12.13 Summary
- •12.14 Problems
- •12.15 Bibliography
- •12.16 References
- •SIMULATION
- •13.1 Types of Simulation
- •13.3 Logic Systems
- •13.4 How Logic Simulation
- •13.5 Cell Models
- •13.6 Delay Models
- •13.7 Static Timing Analysis
- •13.8 Formal Verification
- •13.9 Switch-Level Simulation
- •13.11 Summary
- •13.12 Problems
- •13.13 Bibliography
- •13.14 References
- •TEST
- •14.1 The Importance of Test
- •14.2 Boundary-Scan Test
- •14.3 Faults
- •14.4 Fault Simulation
- •14.6 Scan Test
- •14.7 Built-in Self-test
- •14.8 A Simple Test Example
- •14.10 Summary
- •14.11 Problems
- •14.12 Bibliography
- •14.13 References
- •15.1 Physical Design
- •15.3 System Partitioning
- •15.4 Estimating ASIC Size
- •15.5 Power Dissipation
- •15.6 FPGA Partitioning
- •15.7 Partitioning Methods
- •15.8 Summary
- •15.9 Problems
- •15.10 Bibliography
- •15.11 References
- •16.1 Floorplanning
- •16.2 Placement
- •16.3 Physical Design Flow
- •16.4 Information Formats
- •16.5 Summary
- •16.6 Problems
- •16.7 Bibliography
- •16.8 References
- •ROUTING
- •17.1 Global Routing
- •17.2 Detailed Routing
- •17.3 Special Routing
- •17.5 Summary
- •17.6 Problems
- •17.7 Bibliography
- •17.8 References
- •A.2 VHDL Syntax
- •A.3 BNF Index
- •A.5 References
- •B.2 Verilog HDL Syntax
- •B.3 BNF Index
- •B.4 Verilog HDL LRM
- •B.5 Bibliography
- •B.6 References
10.19 Bibliography
The definitive reference guide to VHDL is the IEEE VHDL LRM [IEEE, 1076-1993]. The LRM is initially difficult to read because it is concise and precise (the LRM is intended for tool builders and experienced tool users, not as a tutorial). The LRM does form a useful reference--as does a dictionary for serious users of any language. You might think of the LRM as a legal contract between you and the company that sells you software that is compliant with the standard. VHDL software uses the terminology of the LRM for error messages, so it is necessary to understand the terms and definitions of the LRM. The WAVES standard [IEEE 1029.1-1991] deals with the problems of interfacing VHDL testbenches to testers.
VHDL International maintains VIUF (VHDL International Users' Forum) Internet Services ( http:/www.vhdl.org ) and links to other groups working on VHDL including the IEEE synthesis packages, IEEE WAVES packages, and IEEE VITAL packages (see also Appendix A).
The frequently asked questions (FAQ) list for the VHDL newsgroup comp.lang.vhdl is a useful starting point (the list is archived at gopher://kona.ee.pitt.edu/h0/NewsGroupArchives ). Information on character sets and the problems of exchanging information across national boundaries can be found at ftp://watsun.cc.columbia.edu/kermit/charsets .
10.20 References
Page numbers in brackets after the reference indicate the location in the chapter body.
IEEE 1029.1-1991. IEEE Standard for Waveform and Vector Exchange (WAVES). IEEE Std 1029.1-1991. The Institute of Electrical and Electronics Engineers, Inc., New York. Available from The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, NY 10017 USA.
IEEE 1076-1993. IEEE Standard VHDL Language Reference Manual (ANSI).
IEEE Std. 1076-1993. The Institute of Electrical and Electronics Engineers, Inc., New York. Available from The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, NY 10017 USA. [p. 380]
IEEE 1076.2-1996. Standard VHDL Language Mathematical Packages. IEEE Ref. AD129-NYF. Approved by IEEE Standards Board on 19 September 1996. [p. 404].
ISO 8859-1. 1987 (E). Information Processing--8-bit single-byte coded graphic character sets--Part 1: Latin Alphabet No. 1. American National Standards Institute, Hackensack, NJ; 1987. Available from Sales Department, American National Standards Institute, 105-111 South State Street, Hackensack, NJ 07601 USA. [p. 391]
IEEE Language Reference Manual project
This material is an experimental project to link ASICs... the book with the IEEE VHDL Language Reference Manual. The VHDL-93 LRM was published on CD-ROM in 1997, but contained errors. The VHDL LRM and the CD-ROM are both copyright material, and vigorously protected by the IEEE. This project is not intended for public distribution and access is therefore protected.
1.The first part of the project was to find/eliminate the errors in the CD-ROM version of VHDL-93 LRM (these have been found and corrected).
2.The second part was to link the LRM with the text (this is complete, see the index of chapters in HTML format)
3.The third part is to merge educational material developed by the US Department of Defence (DoD) DARPA sponsored RASSP project with the LRM and ASICs... the book. Without the support of the IEEE or DARPA, and with no easy resolution to copyright problems, it is currently impossible to complete this project.
●LRM Table of Contents
●LRM Section 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
●LRM Annex A B C D E
●LRM Index
Some notes for people working on and with this project material
References to the IEEE LRM in my HTML pages are of the form:
<A HREF="../LRM/HTML/1076_2.HTM#2.2">93LRM2.2]</A>
to turn these off (so that people cannot access the LRM, for example) you need to insert comment tags around the HTML reference tags:
<!----> and <!---->
Search and replace for HTML (grep format for BBEdit)
search for: </PRE>/r<PRE CLASS="Computer[a-zA-z]+"><A NAME="[^"]+"> </A>
replace with: null
search for: (<PRE CLASS="Computer[^"]+">)<A NAME="[^"]+"> </A>
replace with: \1
search for: </B>/r replace with: </B>
search for: <TABLE>
replace with: <TABLE BORDER="1" CELLSPACING="2" CELLPADDING="2">
search for: <SUB CLASS="Subscript"> replace with: <SUB>
search for: <P CLASS="Symbol">([a-zA-z])</P> replace with: <FONT FACE="symbol">\1</FONT>
search for: <P CLASS="Symbol">¥</P>
replace with: <FONT FACE="symbol">¥</FONT>
Some of the material in this website is protected using access control.
The IEEE VHDL LRM material on which the LRM project is based is copyright and therefore access is protected with the following .htaccess file:
<Limit GET> order deny,allow deny from all
allow from .eng.hawaii.edu allow from 128.171.61 </Limit>
Web-page access control
In order to control access to Web pages, NCSA and Apache servers (and many others) look for a file named .htaccess in each directory along the path to a Web page. The lowest level .htaccess file (i.e. that closest to the Web page) determines access. There are two styles of access control.
Domain-name based access control
The first and simplest type of access control restricts access to machines which have a hostname that match a pattern. For example placing these lines in a file named .htaccess in a directory
Options All
<Limit GET> order deny,allow deny from all allow from .edu </Limit>
restricts access to that directory to those hostnames whose domain names end in
.edu.
Password-based access control
To implement password access control, an .htaccess file looks like this
Options All AuthType Basic AuthName [message] AuthUserFile .passwd <Limit GET>
require valid-user </Limit>
You need a copy of the htpasswd program to establish user names and assign passwords.
The message in the square brackets is a text string that will be displayed to the user when they are prompted for the password. The password file does not have to located in the same directory as the .htaccess file.
For more information, see the NCSA HTTPd access configuration documentation.
Errors in IEEE VHDL CD-ROM
Document titles
The documents all have titles:
VHDL LRMIntroduction
(sometimes this is repeated multiple times) except 1076_TOC.HTM which has the title:
1076 -- Table of Contents
Broken links
20 missing or broken links (from Adobe PageMill 2.0):
Broken links:
Problem: In 3.1.4 and 3.1.4.1 (see below) there are four bad links attached to
the number '1.0'.
Fix: remove the links.
3.1.4 Floating point types
...
An implementation may restrict the bounds of the range constraint of floating point types other than type universal_real. However, an implementation must allow the declaration of any floating point type whose range is wholly contained within the bounds - 1.0 E38 and + 1.0 E38 inclusive. The representation of floating point types must include a minimum of six decimal digits of precision.
NOTE--An implementation is not required to detect errors in the execution of a predefined floating point arithmetic operation, since the detection of overflow conditions resulting from such operations may not be easily accomplished on many host systems.
3.1.4.1 Predefined floating point types
The only predefined floating point type is the type REAL. The range of REAL is host-dependent, but it is guaranteed to include the range - 1.0 E38 to + 1.0 E38 inclusive. It is defined with an ascending range.
Problem: Bad link <A HREF="1076_14.HTM#PED_NUM_SUBT"> in Index (1076_INA.HTM)
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Note: Reference to object is quite far into Section 14.2. It would be better to add another anchor, but this is the simplext fix.
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NOTES
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<A NAME="14.1:NOTES"></A>NOTES
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Fix: change to <A HREF="1076_12.HTM#12.3.1.1">
Problem: bad link in Index (1076_INA.HTM) <A HREF="#12.6.2">
Fix: change to <A HREF="1076_12.HTM#12.6.2">
Problem: bad link in Index (1076_INA.HTM) <A HREF="#4.3.1.3">
Fix: change to <A HREF="1076_4.HTM#4.3.1.3">
Problem: in 1076_9.HTM (see <A HREF="1076_2.HTM#2.6.4">2.6.4
Fix: change to (see <A HREF="1076_12.HTM#12.6.4">12.6.4
Problem: in 1076_AXD.HTM <A HREF="1076_4.HTM#4.3.4">4.3.4
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Fix: change to 4.3.4
Note: There is a Section 4.3.4 Alias Declaration in 1076-87 there is no Section 4.3.4 in 1076-93. There is a Section 4.3.3 Alias declarations in 1076-93.
Problem: in 1076_AXB.HTM <A HREF="1076_7.HTM#7.5.2">7.5.2
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Note: There is no Section 7.5.2. Section 7.4.2 Globally static primaries parts g and h deal with aggregates.
Problem: in 1076_2.HTM <A HREF="1076_8.HTM#8.1.4">8.1.4
Fix: Until I can find out what this is supposed to be, I'll leave it alone.
Note: There is no Section 8.1.4.
Problem: in 1076_AXD.HTM <A HREF="1076_8.HTM#8.3.1">8.3.1
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Fix: change to 8.3.1
Note: There is no Section 8.3.1 in 1076-93. There is a Section 8.3.1 Updating a Projected Output Waveform in 1076-87.
Error in formatting and content in Section 8.
What it currently looks like:
What it should look like:
Minor errors in formatting and content in the Index