B.3 BNF Index

Table B.1 is an index to the 208 Verilog HDL BNF productions, as defined in Annex A of the 95 LRM. For example, to find the legal positions of wait_statement (rule 207) we look up 207 in Table B.1 and find rule 181 ( statement ), which is in turn referenced by rules 1, 56, 64, 89, 133, 166, and 182. Thus we know a wait statement is legal in the following places: always_construct (1), function_declaration (56), initial_construct (64), loop_statement (89), par_block (a parallel block, 133), seq_block (a sequential block, 166), and anywhere statement_or_null (182) is legal. Turning again to Table B.1 (or using the backward-pointing links in rule 182), we find statement_or_null (rule 182) is legal in the following places: 8 ( case_item ), 18 ( conditional_statement ), 148 ( procedural_timing_control_statement ), 191 ( task_declaration ), and 207 ( wait_statement ).

TABLE B.1 Index to Verilog HDL BNF rules (list of rules that reference a rule).

19 19, 20, 67, 109, 126, 132, 145, 146, 153, 158, 161, 175, 177, 179, 189

526, 8, 9, 17, 18, 25, 32, 50, 52, 55, 89, 90, 99, 100, 106, 108, 109, 112, 122, 131, 146, 159, 161, 163, 187, 192, 197, 207

21, 35, 48, 49, 50, 51, 55, 56, 67, 69, 78, 84, 85, 91, 93, 100, 101, 102, 103,

62104, 108, 109, 113, 124, 126, 132, 133, 143, 145, 146, 158, 161, 166, 179, 188, 191, 192, 199, 200, 202, 204

70 12, 45, 98, 116, 118

101 12, 45, 98, 116, 118, 134, 137, 151

126 12, 45, 98, 116, 118, 151 153 66, 68, 101, 102, 104, 107, 123, 154, 160 181 1, 56, 64, 89, 133, 166, 182

Table B.2 is a list of the 102 Verilog HDL keywords in the 95 LRM and an index to the rules that reference these keywords. Note the spelling of the keyword scalared (not scalered). For example, to find out how to use the keyword parameter to define a constant, we look up parameter in Table B.2 to find rule 129 ( parameter_declaration ), which includes a reference to section 3.10 of the 95 LRM. The index in this book will also help (the entry for parameter points you to examples in Section 11.2.4, Numbers, in this case).

There are many Verilog tools currently available that use many versions of the Verilog language. Most tool vendors explain which of the Verilog constructs are supported; many use the 95 LRM BNF syntax in this explanation.

TABLE B.2 Verilog HDL keywords and index (list of rules that reference a keyword).