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8.3.4 Comparison

The halfgate ASIC design illustrates the differences between a nondeterministic coarse-grained FPGA (Xilinx XC4000), a nondeterministic fine-grained FPGA (Actel ACT 3), and a deterministic complex PLD (Altera MAX 7000). These differences, summarized as follows, were apparent even in the halfgate design:

1.The Xilinx LCA architecture does not permit an accurate timing analysis until after place and route. This is because of the coarse-grained nondeterministic architecture.

2.The Actel ACT architecture is nondeterministic, but the fine-grained structure allows fairly accurate preroute timing prediction.

3.The Altera MAX complex PLD requires logic to be fitted to the product steering and programmable array logic. The Altera MAX 7000 has an almost deterministic architecture, which allows accurate preroute timing.

8.4 Summary

The important concepts covered in this chapter are:

FPGA design flow: design entry, simulation, physical design, and programming

Schematic entry, hardware design languages, logic synthesis

PALASM as a common low-level hardware description

EDIF, Verilog, and VHDL as vendor-independent netlist standards

8.5 Problems

* = Difficult, ** = Very difficult, *** = Extremely difficult

8.1(Files, 60 min.) Create a version of Table 8.1 for your design system.

8.2(Scripts, 60 min.) Create a version of Table 8.5 for your design system.

8.3(Halfgate, 60 min.)

a. Using an FPGA of your choice, estimate the preroute delay of a single inverter (including I/O delays).

b. Complete a halfgate design and explain the postroute delays (make sure you know what conditions are being used worst-case commercial, for example).

8.4(***Xilinx die analysis, 120 min.) The data in Table 8.10 shows some

information derived from a die photo of an ATT3020 (equivalent to a Xilinx 3020) in the AT&T data book. The die photo shows the CLBs clearly enough that we can measure their size. Then, knowing the actual die size, we can calculate the CLB size and other parameters. From your knowledge of the contents of the XC3020 CLB, as well as the programming and interconnect structures, make an estimate (showing all of your approximations and explaining all of your assumptions) of the CLB area and compare this to the value of 277 mils 2 shown in Table 8.10 . You will need to calculate the number of logic gates in each CLB including the LUT resources. Estimate how many pass transistors and memory elements are required as well as calculate how many routing resources are assigned to each CLB. Hint: You may need to use the Xilinx software, look at the Xilinx data books, or even the AT&T (Lucent) Orca documentation.

TABLE 8.10 ATT3020 die information (Problem 8.4).

 

Parameter

Specified in data

Measured on die

Calculated from die

book

photo

photo

 

3020 die width

183.5 mil

4.1 cm

 

3020 die height

219.3 mil

4.9 cm

 

3000 CLB width

0.325 cm

14.55 mil = 370 m m

3000 CLB height

0.425 cm

19.02 mil = 483 m m

3000 CLB area

 

 

277 mils 2

3020 pad pitch

 

1.61 mm/pad

7.21 mil/pad

Source: AT&T Data Book, July 1992, p. 3-76, MN92-024FPGA.

8.5 (***FPGA process, 120 min.) Table 8.11 describes AT&T s 0.9 m m twin-tub V CMOS process, with 0.75 m m minimum design rules and 0.6 m m effective channel length and silicided (TiS 2 ) poly, source, and drain. This is the process used by AT&T to second-source the Xilinx XC3000 family of FPGAs. Calculate the parasitic resistance and capacitance parameters for the interconnect.

TABLE 8.11 ATT3000 0.9 m m twin-tub V CMOS process (Problem 8.5).

Parameter

Value

Die thickness, t die

21 mil

Wafer diameter, W D

5 inch

Wafer thickness, W t

25 mil

Minimum feature size, 2 l

0.75 m m

Effective gate length, L eff ( n -channel and p -channel)

0.6 m m

First-level metal, m1

Ti/AlCuSi

Second-level metal, m2

AlCuSi

m1 width

0.9 m m

m2 width

1.2 m m

m1 thickness

0.5 m m

m2 thickness

1.0 m m

m1 spacing

1.0 m m

m2 spacing

1.3 m m

D1 dielectric thickness, boron/phosphorus doped glass

3500 Å

D2 dielectric thickness, undoped glass

9000 Å

Minimum contact size

1.0 m m

Minimum via size

1.2 m m

Isolation oxide, FOX

3500 Å

Gate oxide

150 Å

Source: AT&T Data Book, July 1992, p. 2-37 and p. 3-76, MN92-024FPGA.

8.6 (Xilinx die costs, 10 min.) Table 8.12 shows the AT&T ATT3000 series die information. Assume a 6-inch wafer that costs $2000 to fabricate and has a 90 percent yield. (a) What are the die costs? (b) Compare these figures to the costs of XC3020 parts in 1992 and comment.

TABLE 8.12 ATT3000 die information (Problem 8.6).

 

Die

Die

Die area

Die

 

Die

height

width

area

CLBs

/mils 2

 

/mils

/mils

/cm2

 

 

 

 

3020

219.3

183.5

40,242

0.26

8 ¥ 8

3030

259.8

215.0

55,857

0.36

10 ¥ 10

3042

295.3

242.5

71,610

0.46

12 ¥ 12

Die perimeter

I/O

/mils

pads

806

74

950

98

1076

118

3064 270.9

366.5

99,285

0.64

16 ¥ 14

1275

142

3090 437.0

299.2

130,750

0.84

16 ¥ 20

1472

166

Source: AT&T Data Book, July 1992, p. 3-75, MN92-024FPGA. 1 mil 2 = 2.54 2 ¥ 10 6 cm 2 = 6.452 ¥ 10 6 cm 2 .

8.7 (Pad density) Table 8.12 shows the number of pads on each of the

AT&T 3000 (equivalent to the Xilinx XC3000) die. Calculate the pad densities in mil/pad for each part and compare with the figure for the ATT3020 in Table 8.10

.

8.8 (Xilinx HardWire, 10 min.) Xilinx manufactures nonprogrammable versions of its LCA family of FPGAs. These HardWire chips are useful when a customer wishes to convert to high-volume production. The Xilinx 1996 Product overview (p. 16) shows two die photographs: one, an XC3090 (with the four quadrants of 8 ¥ 10 CLB matrices visible), which is 32 mm ¥ 47 mm; the other shows the HardWire version (24 mm ¥ 29 mm). Estimate the die size of the HardWire version from the data in Table 8.12 and estimate the percentage of a Xilinx LCA that is taken up by SRAM.

Answer: 60,500 mils 2 ; 50 %.

8.9(Xilinx XDE, 10 min.) During his yearly appraisal Dewey explains to you how he improved three Xilinx designs last year and managed to use 100 percent of the CLBs on these LCA chips by means of the XDE manual place-and-route program. As Dewey s boss, rank Dewey from 1 (bad) to 5 (outstanding) and explain your ranking in a space that has room for no more than 20 words.

8.10(Clocks, 60 min) (From a discussion on an Internet newsgroup including comments from Peter Alfke of Xilinx) Xilinx guarantees that the minimum value for any delay parameter is always more than 25 % of the maximum value for that same parameter, as published for the fastest speed grade offered at any time. Many parameters have been reduced significantly over the years, but the clock delay has not. For example, comparing the fastest available XC3020-70 in 1988 with the fastest available XC3020A-6 (1996):

logic delay ( t ILO ) decreased from 9 ns to 4.1 ns

output-to-pad delay decreased from 10 ns to 5 ns

internal-clock-to-output pad delay decreased from 13 ns to 7 ns

The internal speed has more than doubled, but the worst-case clock distribution delay specification has only changed from 6.0 ns (1988) to 5.7 ns (1996).

Comment on the reasons for these changes and their repercussions.

8.11(State-machine design)

a. (10 min.) Draw the state diagram for the LOG/iC code in Table 8.2 .

b. (10 min.) Show, using an example input sequence, that the detector

works.

c. (10 min.) Show that the state equations and the encoding for the PALASM code in Table 8.2 correctly describe the sequence detector state machine.

d. (30 min.) Convert this design to a different format of your choice: schematic, low-level design language, or HDL.

e. (30 min.) Simulate and test your design.

8.12(FPGA software, 60 min.) Write a minitutorial (less than 2 pages) on using your FPGA design system. An example set of instructions for the Altera

MAX PLUS II software on a Unix system are shown below:

Setup:

1.Copy ~altera/M+2/maxplus2.ini into ~you/yourDirectory (call this the working directory).

2.Edit maxplus2.ini and point the DESIGN_NAME to your design

3.Copy ~altera/M+2/compass.lmf and ~altera/M+2/compass.edc into your working directory.

4.Copy ~altera/M+2/foo.acf into your working directory and rename it mydesign.acf if your design name is mydesign.edf .

5.Set the environment as follows:

setenv LM_LICENSE_FILE ~altera/maxplus2/adm/license.altera

set path=($path ~altera/maxplus5.1/bin)

and run the programs in batch mode: maxplus2 -c mydesign.edf . Add to this information on any peculiarities of the system you are using (handling of overwriting of files, filename extensions and when they are created, arguments required to run the programs, and so on).

8.13 (Help, 20 min.) Print the help for the key programs in your FPGA system and form it into a condensed cheat-sheet. Most programs echo help instruction when called with a '-help' or '?' argument (this ought to be a standard). For example, in the Actel system the key programs are edn2adl, adl2edn, and als (in newer versions adl2edn is now an option to als). Hint: Actel does not use '-help' argument, but you can get instructions on the syntax for each option individually. Table 8.13 shows an example for the Xilinx xdelay program.

TABLE 8.13 Xilinx xdelay arguments.

usage: xdelay [<options>] [<lcafile> ..] where <options> are:

-help Print this help.

-timespec Do timespec based delay analysis. -s Write short xdelay report.

-x Write long xdelay report.

-t <template file> Read <template file>.

-r Use two letter style block names in output. -o <file> Send output to file.

-w Write design file, after retiming net delays. -u <speed> Use the <speed> speed grade.

-d Don't trace delay paths.

-convert <input .lca file> <new part type> <output .lca file> Convert the input design to a new part type.

Specify no arguments to run xdelay in interactive mode.

To Select Report Specify Option

------------------------- ---------------------------

TimeSpec summary -timespec

Short path details -s

Long path details -x

Analyze summary none of -s, -x or -timespec

A template file can be specified with the -t option to further filter the selected report. Only those template commands relevant to the selected report will be used.

Using -w and -d options together will insert delay information into the design file(s), without tracing any paths.

The -convert option may not be used with any other options.

Last Edited by SP 14112004

LOW-LEVEL

DESIGN ENTRY

The purpose of design entry is to describe a microelectronic system to a set of electronic-design automation ( EDA ) tools. Electronic systems used to be, and many still are, constructed from off-the-shelf components, such as TTL ICs. Design entry for these systems now usually consists of drawing a picture, a schematic . The schematic shows how all the components are connected together, the connectivity of an ASIC. This type of design-entry process is called schematic entry , or schematic capture . A circuit schematic describes an ASIC in the same way an architect s plan describes a building.

The circuit schematic is a picture, an easy format for us to understand and use, but computers need to work with an ASCII or binary version of the schematic that we call a netlist . The output of a schematic-entry tool is thus a netlist file that contains a description of all the components in a design and their interconnections.

Not all the design information may be conveyed in a circuit schematic or netlist, because not all of the functions of an ASIC are described by the connectivity information. For example, suppose we use a programmable ASIC for some random logic functions. Part of the ASIC might be designed using a text language. In this case design entry also includes writing the code. What if an ASIC in our system contains a programmable memory (PROM)? Is the PROM microcode, the '1's and '0's, part of design entry? The operation of our system is certainly dependent on the correct programming of the PROM. So perhaps the PROM code ought to be considered part of design entry. On the other hand nobody would consider the operating-system code that is loaded into a RAM on an ASIC to be a part of design entry. Obviously, then, there are several different forms of design entry. In each case it is important to make sure that you have completely specified the system not only so that it can be correctly constructed, but so that someone else can understand how the system is put together. Design entry is thus an important part of documentation .

Until recently most ASIC design entry used schematic entry. As ASICs have become more complex, other design-entry methods are becoming common. Alternative design-entry methods can use graphical methods, such as a schematic, or text files, such as a programming language. Using a hardware description language ( HDL ) for design entry allows us to generate netlists directly using logic synthesis . We will concentrate on low-level design-entry methods together with their advantages and disadvantages in this chapter.

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